3:30pm - 3:50pm
High Voltage: 1
Influence of Low Pressure on Thermal Limit of MVDC Power Cables Used in All Electric Aircraft
1Virginia Tech, United States of America; 2University of New Mexico, United States of America
An electric power system (EPS) with high power delivery and low system mass is required for wide-body all-electric aircraft (AEA). Cables are an essential component of this future EPS. The pressure at the cruising height of a wide-body aircraft is around 18.8 kPa. At that pressure, heat transfer to the ambient air by convection is strongly limited, so the temperature field distribution across the aircraft cables is expected to be different from atmospheric pressure. The temperature field across the cable depends on the velocity field of the ambient air, which is a function of pressure and temperature. Also, to obtain the electric field of the DC cables in the electric aircraft power system, the conductivity of the insulation, a function of temperature and electric field, should be calculated. Therefore, a coupled multi-physics study should be conducted to calculate the temperature field and electric field across the cable. In this paper, a 5 kV DC cable is studied at 18.8 kPa pressure to compare the cable's temperature field and electric field at low pressure to the atmospheric pressure. The voltage level considered was resulted from our previous studies where we proposed new EPS architectures for a wide-body AEA. Moreover, the maximum permissible flowing current of the cable is investigated at the pressure of 18.8 kPa regarding the thermal limits of the cable. It is shown that at low pressures the temperature of the cable is highly increased compared to atmospheric pressure, so the maximum permissible flowing current is lower than the rated current.
3:50pm - 4:10pm
High Voltage: 2
An innovative approach to the design of medium voltage power electronics printed circuit-boards
Center for Advanced Power Systems, Florida State University, United States of America
Going towards maximization of power density and dynamics, the supply of electrical and electronics components in industrial, electrified transportation and renewable electrical assets is shifting from sinusoidal AC to modulated AC and DC, involving voltage and load transients.
Voltage is increasing to the MV range so that power electronics boards must be designed to withstand, for the specified operation life, high electric fields and temperatures. Very fast switching time and high modulation and carrier frequencies have to be also managed.
This determines electrical, thermal and mechanical stress profiles which can change significantly with supply voltage and time. They can affect (increasing) electrothermal and mechanical aging rate regarding both intrinsic and extrinsic aging factors.
As an example, the electric field in bulk insulation defects or on the PCB surface can incept partial discharges, PD, for some stress conditions, with different PD amplitude and repetition rate from AC to DC. This impacts on extrinsic aging rate, so that life reduction can be dramatic even if PD activity would be discontinuous.
This paper introduces an innovative approach to power electronic board design which should allow an optimized design of PCB insulation systems as regards their reliability, life, shape and dimensions/weight, taking into account the risk of generating extrinsic aging phenomena. The so called “three-leg approach” is based on the comparison and match of results coming from electric stress profile simulation, discharge modelling and partial discharge, PD, measurements under the type of waveform that a PCB can experience, specifically modulated AC and DC. It consists of extracting the information of maximum bulk and surface (tangential) electrical stress (field) at operating temperatures, comparing them with models for partial discharge inception that associated the stress to PD likelihood and linking such results with PD measurements (particularly the partial discharge inception voltage, PDIV). This would provide a PD-free design allowing inference on connector technology and shape, as well as quantities as creepage and clearance. The focus in this paper is describing how to deal with the first leg approach on a 5 kV PCB, showing electric field simulation results and explaining how discharge modelling and PD measurement will complete the whole optimized design.
4:10pm - 4:30pm
High Voltage: 3
Breakdown Characteristics of Printed Circuit Board Based Transformer Windings
1QinetiQ, United Kingdom; 2University of Southampton, United Kingdom
Further to work presented at IPMHVC 2018 , this paper examines printed circuit board (PCB) based transformer winding technology that can be used in a new generation of UHV power supply. Transformer windings printed on PCBs have several advantages over conventional windings. In addition to being robust and convenient to handle, they are easy, and relatively cheap, to manufacture. For these reasons they have enjoyed limited use in low voltage applications.
4:30pm - 4:50pm
High Voltage: 4
Reliable, Low-Jitter 100-kV Trigger Generator
R. E. Beverly III and Associates, United States of America
Large pulsed power systems require multiple trigger generators that are synchronous and accurate. Spark gaps having up to 200 kV across the electrodes are often utilized. Precise system triggering requires a comparable open-circuit peak voltage for low jitter operation and high certainty of gap commutation. "Low jitter" is typically σ ≤ 3 ns relative to a fast rise, 5-V command signal. One standard deviation σ is calculated using sampled delay-time measurements, where td is defined as the time between the leading edges of the input command and generator output signals.
The trigger generator must be highly reliable. Large systems carry enough energy to damage the load or other components even if one sub-module unintentionally pre-fires. Large systems are also degraded by misfires because most experiments have specific requirements for amplitude and temporal shape of the load current. Collectively these constraints place severe demands on trigger generators.
In simplest terms, the problem is one of amplification of the command pulse with a power gain of ~85 db. In practice, this must be done in multiple steps. In our approach, the command pulse is amplified to ~1 kV using a proprietary solid-state driver. Voltage multiplication is accomplished by a four-stage inductive adder that provides a fast-rise (17 ns) trigger pulse for a highly-compact (21 kg), 3-stage Marx generator with 19 J of stored energy. The first stage is configured as a trigatron with a surface discharge trigger.
The load (field-distortion switch, railgap, etc.) is connected through either a 6-m RG-220/U or 21-m RG-218/U coaxial cable. When driving a cable matched load (50 Ω), the peak voltage is ≈100 kV with a rise time <5 ns and e-folding time ≈150 ns. A peak voltage of 180 kV, rise time of <3 ns, and e-folding time of 190 ns are observed with a higher-impedance load (190 Ω). The self-break fraction (f) is defined as the ratio of Marx generator operating voltage (Vop) and median self-breakdown voltage (Vsb), where Vsb is a function of the internal gas pressure. td decreases rapidly to a lower asymptote as f→1 and σ < 4 ns when f ≥ 0.83. The probability of a pre-fire is extremely low as long as f ≤ 0.90, therefore the trigger generator affords both low jitter and high reliability when operating within the recommended range 0.85 ≤ f ≤ 0.89.
Compared with other commercially-available trigger generators, our design does not rely upon bulky and difficult-to-obtain thermionic devices (e.g. thyratrons). The design is fully scalable to higher voltages by incorporation of additional Marx stages and scalable to higher energies by increasing the number of capacitors per stage. The output polarity may be changed by the user. The control console accepts both fiber-optic and electrical command inputs. The trigger generator is largely impervious to load faults when properly coupled. The system is designed for long life with minimal maintenance.
4:50pm - 5:10pm
High Voltage: 5
Custom electrostatic probe diagnostics
1Texas Tech University, United States of America; 2Pantex, Amarillo Tx. United States of America
A custom electrostatic probe design for the mapping of surface charge is presented. The coaxial geometry capitalizes on capacitive voltage division, allowing for a simple design and rapid prototyping abilities. Previously a coaxial probe was designed with a 9.4 mm diameter inner conductor to reduce field enhancements to surpass commercially available probe thresholds of +/- 20 kV. Designing the inner conductor to reduce field enhancements that could reach +/- 30 kV at 1 cm distances in air resulted in a reduced resolution compared to commercially available probes when compared directly without post-processing. This work focuses on an updated design where the inner conductor diameter was reduced to 1.6 mm, yielding an improved resolution by a factor of approximately six. The outer conductor was wrapped around the center conductor to keep the field enhancement low, leaving only an ~ 0.5 mm insulating gap between the outer, grounded conductor and the center. This effectively created a hemispherical ending with a 9.4 mm diameter since the potential difference between inner and outer conductors is only on the order of a few volts.
A post-processing procedure using an Inverse Wiener filter, often used in image processing, deconvolves the custom probe’s response and regains some of the resolution lost through the necessarily large distance from the charged surface. A COMSOL finite element simulation was used to find the spatial transfer function needed for the post-processing correction. Surface charge mapping was performed for both PTFE and Acrylic, focusing on how charging polarities and different humidities affect charge distribution to determine a relationship between charge decay and unique charge distributions. For instance, using the same triboelectric charging technique for PTFE and Acrylic resulted in negative and positive surface charging, respectively, as expected from the triboelectric series. Across the measured RH humidity range, ~ 10 to 60%, Acrylic had a slower decay rate than PTFE, which may be primarily driven by the initially higher surface potential magnitude observed for PTFE under triboelectric charging.
5:10pm - 5:30pm
High Voltage: 6
Improved Manufacturing Process for High Voltage Pulsed Diodes
1University of Missouri-Kansas City, United States of America; 2Semiconductor Power Technologies, Manhattan, KS, USA
DSRDs - Drift Step Recovery Diodes are used as opening switches for pulse generators since 1960s. Deep diffusion into a thinned wafer have been mostly used for the DSRD fabrication. The diffusion-based process has limitations in: (1) doping profile optimization, (2) diode side surface termination, (3) diode side surface passivation, (4) stacking on wafer level. These features limit final diode performance. (1) long voltage rise time, (2) and (3) low diode breakdown voltage, (4) heavy labor at die assembly into stacks.
We have suggested and tested new DSRD fabrication scheme where (1) deep diffusion replaced by epitaxy with desired doping profile, (2) diode side termination done by anisotropic etch instead on mechanical sawing, (3) diode side passivation by silicon dioxide instead on polyimide, (4) stacking on wafer level.
TCAD simulation predicted an optimal DSRD doping profile to reach the shortest rise time on a load. The predicted profile is different from profile obtained by diffusion (complementary error function). The predicted profile can be copied into silicon by controlling dopant flow during epitaxy. We have modified epitaxy tool to achieve desired profile and successfully grown near 200-micron thick epitaxial layer. This is drastically different from known attempts to fabricate DSRD using non-controlled (flat) epitaxial doping profile.
In traditional DSRD technology, wafers are cut into diode dies mechanically - by sawing, waterjet, laser cut, etc. This result in termination of diodes by surface that is perpendicular to wafer surface (vertical wall). While beveled wall is preferable – it gives higher breakdown voltage. Thus, traditional DSRD has breakdown along the vertical wall - diode termination surface. Also, mechanical cutting inevitably produces cracks, up to 50 microns deep into silicon. These additionally lower the breakdown voltage. And requires chemical etching, typically in HNA – to dissolve the damaged silicon.
We have replaced mechanical cutting step by anisotropic etching of v-grooves through lithography mask. Advantages are beveled diode side termination wall and no cracks. These result in higher breakdown voltages of the diodes. Another advantage is – v-groves go only below the epitaxial p-n junction layers, but not to the bottom of silicon substrate. Therefore, wafer integrity is preserved. This gives us an opportunity to stack wafers, not individual dies. Finally, we get more then hundred times smaller number of stacking operations, i.e., better manufacturability.
Passivation in the traditional DSRD process is heavily restricted. Say, oxidation cannot be used as top, and bottom of diode dies are already covered with metal layers for Ohmic contacts. Therefore, polymer coating – polyimide or silicone used. Our v-groove diode die separation does not pose this limitation. We have option to deposit metals later in process flow. Therefore, we use thermal oxidation to passivate side surfaces of individual diodes. The silicon dioxide passivation is preferable compared to polymer coating in both, breakdown voltage and long-term device stability considerations.
DSRDs manufactured with our novel process are sent for measurement of their pulsed performance. Separate presentation will report comparison of pulsed performance between traditional and our DSRDs.