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Session Overview |
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| 8:30am - 6:00pm |
Pre-Registration |
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| 9:00am - 1:00pm |
SC 1: Short Course "Advanced Substrates for Chiplets, Heterogeneous Integration, and Co-Packaged Optics" Short Course Instructor: John Lau, Unimicron Technology Corporation |
SC 2: Short Course "Microelectronics packaging basics in practice!" Short Course Instructor: Valerie Volant, STMicroelectronics |
SC 3: Short Course Further information will follow shortly. |
| 2:00pm - 6:00pm |
SC 4: Short Course "From Wafer to Panel Level Packaging" Short Course Instructors: Tanja Braun & Markus Wöhrmann, Fraunhofer IZM |
SC 5: Short Course "Electronic/Photonic Convergence Using Advanced Packaging: A Status" Short Course Instructor: Stéphane Bernabé, CEA LETI |
SC 6: Short Course Further information will follow shortly. |
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| 9:00am - 9:10am |
Welcome & Conference Opening |
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| 9:10am - 9:55am |
Keynote 1 Location: Amphitheatre "Propelling AI forward through Advanced Packaging Creativity" by Ingu Yin Chang (Executive Vice President, ASE Inc.) |
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| 9:55am - 10:40am |
Keynote 2 Location: Amphitheatre "The Interconnect 'Panelization'" by Laurent Herard (Group VP – Head of Back End Manufacturing & Technology R&D, STMicroelectronics) |
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| 10:40am - 11:15am |
Break – Exhibition |
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| 11:15am - 12:30pm |
S 1A: IC Packaging Location: Amphitheatre Development of Die Attach Process for Thin Device Using a Novel High Thermal Conductivity Pressure-less Semi-sintering Paste with Capillary Filling Technology A Novel Package Technology for Better MOSFET Performance Fan Out Wafer Level Packaging – Towards a European Manufacturing Supply Chain |
S 1B: Intreconnection Technologies Location: Kilimandjaro Material Strategy and Challenges for Fine Interconnection in Advanced Packages Stability of the Superconducting β-Sn Phase at Low Temperatures for 3D Cryogenic Packaging Integration of Photo-imaging Technology and Microvias in LTCC for Enhanced High-frequency Applications and Packaging |
S 1C: Quality and Reliability Location: Mont Blanc Study of a Failure of a Compact Ceramic No-lead Package Due to Tinning Induced Thermal Shock and Its Design Improvement Assessment of QFN Assemblies’ Thermal Strain Characterization and its Evolution Through Thermal Cycling Aging Embedding of components as an effective way to achieve high reliability for special applications products |
S 1D: Assembly and Manufacturing Location: Makalu Development of Advanced Screen-printing Technology for Flip-chip Transfer of Electronic Components Thinning and Dicing Process Integration of High Accuracy Using A Novel Self-assembly Stage for Chip on Wafer A Study of 355 nm UV Laser Ablation Process for Singulation of Silicon Wafers |
| 12:30pm - 1:50pm |
Lunch – Exhibition |
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| 1:50pm - 3:05pm |
S 2A: Interconnection Technologies Location: Amphitheatre Characterization of Chip-to-wafer Interconnects with Thick Gold Finish for Fan-out Wafer-level Packaging RDL First Integration Fine-pitch Die-to-wafer Bonding Technologies for Chiplet Integration Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die |
S 2B: Design, Modelling and Simulation Location: Kilimandjaro A Methodology for Modeling Capillary Underfill (CUF) in Advanced Packaging Simulation-based Analysis of Thermal Effects Induced by RF Interference in MEMS Microphones Numerical Case Study of Stress and Plastic Strain Distributions in BGA Solder Balls by Comparison of a Novel Inorganic Encapsulation and Conventional Underfill Variants |
S 2C: System in Package Location: Mont Blanc Research on Damage Behaviour of Vertical Interconnection Solder Joints in a RF SiP Module A Miniaturized Dual Band (28/39 GHz) AiP Design for Millimeter-Wave 5G Mobile Phone Applications Development of a 3D Quilt Packaging Method for Implantable Applications |
S 2D: Materials Location: Makalu Bi–in Segregation in Low-temperature SLID Bonding: Au-in-bi System Large Area (> 2500mm²) Sintering at Sub 220°C With Micro-scale Copper Flakes Influence of Total Encapsulation of White-light Mid-power LED Packages Over the Correlated Colour Temperature |
| 3:05pm - 3:40pm |
Break – Exhibition |
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| 3:40pm - 4:25pm |
Keynote 3 Location: Amphitheatre "Mass Transfer: How the Push for MicroLED Displays Opens New Paths to Heterogeneous Integration" by Dr. Chris Bower (CTO and co-founder, X Display Company (XDC)., Inc.) |
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| 4:25pm - 4:35pm |
Room Change |
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| 4:35pm - 5:50pm |
S 3A: Materials Location: Amphitheatre Exploration of Cu Interfacial Engineering to Enhance Cu Interconnects Reliability Tailored Polymers for Wafer-level Optics Manufacturing via Nanoimprint Lithography Evaluations of Transient Liquid Phase Joints Using In-coated Ag Sheet |
S 3B: Power Electronics Location: Kilimandjaro Promoting EMC Adhesion to Copper Leadframe Through Oxide Thickness Optimization Thermal and Structural Analysis of GaN Layers on Foreign Substrates for Vertical Power Devices The next generation die top system (Ag-only DTS®) for Cu wire bonding on SiC chips |
S 3C: Qulaity and Reliability Location: Mont Blanc The Effect of Solder Die Attach Voids on the Junction-to-case Thermal Resistance of MOSFET Packages Experimental and Numerical Investigation of the Impact of Surface Roughness of Copper Plated through Holes on Thermomechanical Reliability The Impact of Processing Conditions on Bond Reliability in Pressureless Silver Sintering |
S 3D: Assembly and Manufactuirng Location: Makalu A New Carrier Tape for Direct Transfer Bonding (DTB) Process with Ultra-thin Chips Ultra-precise Dispensing for High-resolution Redistribution Layers and 3D Interconnects in Advanced Packaging Applications Plasma Influence for Polymer Uniform Spreading on Heterogeneous Surfaces |
| 6:00pm - 7:30pm |
Dinner: Tasting of regional products & Exhibitors' time (TBC) |
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| 9:00am - 9:45am |
Keynote 4 Location: Amphitheatre "Recent Trends in Automotive Power Module Designs and Technology for Traction Inverters" by Dr. Uwe Hansen (VP Power Component Development, Bosch) |
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| 9:45am - 10:30am |
Keynote 5 Location: Amphitheatre "System Technology Co-optimization for Advanced 3D & Heterogeneous Integration" by Sébastien Dauvé (CEO, CEA-Leti) |
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| 10:30am - 11:15am |
Break – Posters – Exhibition |
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| 11:15am - 12:30pm |
S 4A: Assembly and Manufacturing Location: Amphitheatre In-situ Plasma Monitoring Study for Wire Bonding Process Improvements Impact and Control of Residual Stress in Ceramic Packages Wafer dicing technique for close-butted assemblies |
S 4B: Design, Modelling and Simulation Location: Kilimandjaro Intelligent Prediction of Warpage in Molded fcBGA Packages: An Optimization and Modeling Approach Comparative FEA Analysis of Cu Clip and Al Wire Bonding in Power Discrete Packages Investigation of thermal performance of various thermal interface materials used in top-side-cooled MOSFETs |
S 4C: IC Packagimg Location: Mont Blanc Impact of PFAS Removal on the Harsh Environment Reliability of Semiconductor Packaging FC-LGA for Power Devices: Peculiarities and Challenges Compared with Digital Products Modular Integration of Sensor-Chiplets using Rapid Prototyping including Interconnects and Protective Waveguide Packaging |
S 4D: POSTER SESSION #1 Location: Makalu Thermomechanical Study for Stress-management of Silicon Photonics Interposers Study on the Influence of Reflow Soldering on the Reliability of Mixed Solder Joints Reusing SMD Components on E-textiles: An Ageing Study by Combination of Corrosive Gases and Washing A Comparative Study of Silver Sintering Pastes for Die-attach Applications: Microstructure, Mechanical Properties, and Reliability Design and Evaluation of a Perforated Dielectric Flat Lens Antenna Array for D-band Applications A High Gain Antenna-in-Package (AiP) with Horn Structure for D-band Applications Fine-pitch Flip-chip Bonding Process with Laser Non-conductive Paste (NCP) and Laser-assisted Bonding (LAB) for High-reliability Electrochemical Analysis Reveals Effective Grain Refinement in Copper Electroplating Indium as the Superconducting Interconnect for Quantum Chiplets Test Equipment for Sensor Interfaces Emulated by Generic Electronic Control Unit Visualizing Vibrations of Electronic Modules in Test Grain Orientation Analysis for Thermal Cycling Evaluation of Die-attach Solder Joints Thermal Fatigue Resistance Improvement of New Al Bonding Wire Thermal Analysis of Power Electronic Modules with Parametric Model Order Reduction |
| 12:30pm - 1:50pm |
Lunch Break – Posters – Exhibition |
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| 1:50pm - 3:30pm |
S 5A: Substrate Technologies Location: Amphitheatre Approach for Extracting the Relative Permittivity of Sol-gel Using a Ring Resonator Fabricated on an LTCC Substrate Insulation Layers on Copper Surfaces of Ceramic Circuit Boards for Smart Power Modules Optimized Castellated Hole Interconnects for Ceramic-based Modular Millimeter-Wave Applications up to 85 GHz Glasses as substrates for packaging: Remarks on mechanic reliability. |
S 5B: Optoelectronics Location: Kilimandjaro Precise Alignment and Laser-assisted Bonding of Multichannel Laser Diode Chips for Silicon Photonics Integration Assembly Perspectives on Flip-chip Integration of 1x, 4x and 8x Array InP-SiN Hybrid Laser Devices to Si Photonics Wafers with Sub-500 nm Misalignment TSVs Mechanical Stress Measurements on Silicon Wave-guide Using Phase Shift Interferometry Package and Process Development of Molded Image Sensor Package |
S 5C: Emerging Technologies Location: Mont Blanc TBM-free Plasma Etch Die Singulation Anti-counterfeit Semiconductor Package Using a Unique Identification Mark Metal Oxide Reduction Using Inline Openair-plasma Process to Enhance Adhesion and Improve Durability in Electronics Surface Conditioning of LTCC Substrates for Improved RF Signal Propagation |
S 5D: POSTER SESSION #2 Location: Makalu Microelectronic Packaging Challenges for Stacked Superconducting Qubit Chips Using Indium Bump Bonding Flip-chip Bonded Hybrid Germanium X-ray Detectors Suitable for Operating with Thermal Gradient Between Sensor and ASIC Thermal Management of an Electronic Module Made by a Solderless Assembly Method Selective Micro Laser Melting: Influence of Scan Speed and Laser Power on Interconnect Morphology and Performance Flip Chip Bonding of PMUT Using Adhesives and their Effect on Electrical Performance Automated Non-destructive Mechanical Testing of Fine Pitch Wirebond Arrays Advanced Underfill Developments Enabling Complex AI and HPC Package Designs Advanced Dielectric Films for Fusion Bonded 3D Integration Printable non-volatile and volatile memristors based on Lead-Free Perovskites for artificial synapses and neurons emulation Power modules: Crack and shrinkage phenomenon Void inspection using stress field imaging in densely patterned bonded wafers Photoresist/polymer removal optimized chemistry with adding hydrogen radical in MEMS process fabrication and other applications with HDRF® Innovative deposition solution for TSV integration and conformal deposition of oxide, nitride, and metal layer with dual frequency pulsed equipment, application of low temperature deposition of dielectric layer Temperature Profile Optimization for Vacuum Soldering of Components on Heat Sink Investigating the Dynamic Bending Behaviour of Biodegradable Printed Circuit Boards Stacked and Staggered Vias in FR4 laminate for special application Engineering Dual Alloy Solder Paste Systems to Achieve High Reliability, Energy Savings, Withstand High Junction Temperatures Warpage Reduction of Laminate Substrates Through Metamodel-based Optimization of Material Properties |
| 3:30pm - 4:05pm |
Break – Posters – Exhibition |
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| 4:05pm - 5:20pm |
S 6A: System in Package Location: Amphitheatre Highly Integrated Low Power Wireless Sensor Node Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration RF Characterization of Microscale Transmission Lines on Polymer-based Silicon Interposers for HPC Applications |
S 6B: Quality and Reliability Location: Kilimandjaro Advanced Defects Repair Techniques for Enhancing Yield in Packaging Architectures Prognostics and Health Monitoring: Case Study of a Light Rail Vehicle Power Converter Assembly Optimizing Ag Paste Thickness for Reliable Power Module Packaging |
S 6C: Materials Location: Mont Blanc Ag-nodule Mediated Bonding Using Liquid Quenched Ag-Si Alloy Thermal Characterization of Electrically Conductive Adhesives and Pressureless Sinter Pastes – Comparison of Data Sheet and Real Application Characterisation and Modelling of Sintered Joints Used in Power Electronics |
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| 5:45pm | Bus transfer: Busses leaving venue for confernce dinner |
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| 7:00pm - 10:00pm |
Conference Dinner |
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| 8:45am - 9:30am |
Keynote 6 Location: Amphitheatre "Advanced Packaging – The Key Technology for Chiplet Integration" by Prof. Dr.-Ing. Ulrike Ganesh (Managing Director, Fraunhofer IZM) |
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| 9:30am - 9:40am |
Room Change |
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| 9:40am - 10:55am |
S 7A: Smart Manufacturing Location: Amphitheatre Process Development for Cu Metallization on SiC MOSFETs with Inkjet Printing Technology Development of a Novel Pure-ag-sintering Paste for a Jet-dispensing Process to Achieve Highest Possible Conductivity for Miniaturized Electronic Components with a Pressure-less Sintering Process Additive Manufacturing of High-Performance Ceramics for Fabricating Single- and Multi-Material Components |
S 7B: IC Packaging Location: Kilimandjaro "Advanced Packaging" — A must for the Next-Gen AI and HPC Hardware ! And not Only ! Advancing IC Substrate Manufacturing: Overcoming Challenges and Exploring Opportunities with 10µm Line/Space Technology Heterogeneous Integration and Wafer-level Packaging by Micro-transfer-printing |
S 7C: Intreconnection Technologies Location: Mont Blanc A Novel Photo-patternable Epoxy Flux Material for A New Horizon in Fine Pitch Flip-chip Interconnections Femtosecond Laser Drilling Technologies for Through Glass Via (TGV) Fabrication in Customised Glass Interposers Integration Technology Development of Chip-Antenna Interface for Short Range mmWave Wireless Communication |
S 7D: Inspection and Test Location: Makalu Key Technologies and Design Aspects for Advanced FOCoS Packaging Lensless Through-silicon Microscopy System for Precise Alignment in Photonic Integration Processes Investigating the Role of Thermal Effects in RF Immunity of MEMS Microphones |
| 10:55am - 11:30am |
Break – Exhibition |
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| 11:30am - 12:45pm |
S 8A: Quality and Reliability Location: Amphitheatre Defining a Scalable Test Methodology to Deliver High Quality AI Products Microstructural Characterization for the Joining Interface of Ag@Si Composite Sinter Joining for SiC Power Device by Scanning Transmission Electron Microscopy SACN doped solder balls alloys aging impact on BGA's reliability performance |
S 8B: Assembly and Manufcaturing Location: Kilimandjaro High density 3D interconnections for high performance CdTe based X-rays detectors Atmospheric Plasma Cleaning of Copper Oxide and Tin Oxide for Flux-Free Interconnect Bonding A single step process for Die-attach and substrate-attach with pressure assisted sintering to face harsh conditions |
S 8C: Power Electronics Location: Mont Blanc Measurements at High Temperature for Thermal Resistance of MOSFETs Influence of Uneven Chip Solder Layer Thickness on the Reliability of Power Modules Reliability Evaluation of Direct Bonding for SiC Power Devices by Power Cycling Test |
S 8D: Materials Location: Makalu Understanding Solder Creepage in Thin Si Devices Through Advanced Traceability Systems Enhancing the Reliability of Harsh Environment Electronics Through PFAS-free Multilayer ALD + Parylene Coatings Insulation Materials for Advanced Packaging Applications |
| 12:45pm - 2:00pm |
Lunch – Exhibition |
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| 2:00pm - 2:45pm |
Keynote 7 Location: Amphitheatre "Charting a Path for the Chiplet Era and Beyond" by Craig Bishop (Chief Technology Officer, Deca Technologies) |
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| 2:45pm - 3:15pm |
Awards and Closing Location: Amphitheatre |
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