The 25th European Microelectronics &
Packaging Conference (EMPC 2025)
16 – 18 September 2025
World Trade Center, Grenoble | France
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview |
Date: Monday, 15/Sept/2025 | |
8:30am - 6:00pm | Pre-Registration |
9:00am - 1:00pm | SC 1: Short Course "Advanced Substrates for Chiplets, Heterogeneous Integration, and Co-Packaged Optics" Short Course Instructor: John Lau, Unimicron Technology Corporation |
9:00am - 1:00pm | SC 2: Short Course "Microelectronics packaging basics in practice!" Short Course Instructor: Valerie Volant, STMicroelectronics |
9:00am - 1:00pm | SC 3: Short Course Further information will follow shortly. |
2:00pm - 6:00pm | SC 4: Short Course "From Wafer to Panel Level Packaging" Short Course Instructors: Tanja Braun & Markus Wöhrmann, Fraunhofer IZM |
2:00pm - 6:00pm | SC 5: Short Course "Electronic/Photonic Convergence Using Advanced Packaging: A Status" Short Course Instructor: Stéphane Bernabé, CEA LETI |
2:00pm - 6:00pm | SC 6: Short Course Further information will follow shortly. |
Date: Tuesday, 16/Sept/2025 | |
9:00am - 9:10am | Welcome & Conference Opening |
9:10am - 9:55am | Keynote 1 Location: Amphitheatre "Propelling AI forward through Advanced Packaging Creativity" by Ingu Yin Chang (Executive Vice President, ASE Inc.) |
9:55am - 10:40am | Keynote 2 Location: Amphitheatre "The Interconnect 'Panelization'" by Laurent Herard (Group VP – Head of Back End Manufacturing & Technology R&D, STMicroelectronics) |
10:40am - 11:15am | Break – Exhibition |
11:15am - 12:30pm | S 1A: IC Packaging Location: Amphitheatre |
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Development of Die Attach Process for Thin Device Using a Novel High Thermal Conductivity Pressure-less Semi-sintering Paste with Capillary Filling Technology 1Sumitomo Bakelite Co., Ltd.; 2STMicroelectronics A Novel Package Technology for Better MOSFET Performance Nexperia, United Kingdom Fan Out Wafer Level Packaging – Towards a European Manufacturing Supply Chain 1AEMtec GmbH, Germany; 2Fraunhofer IZM, Germany |
11:15am - 12:30pm | S 1B: Intreconnection Technologies Location: Kilimandjaro |
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Material Strategy and Challenges for Fine Interconnection in Advanced Packages Resonac Stability of the Superconducting β-Sn Phase at Low Temperatures for 3D Cryogenic Packaging Cea, France Integration of Photo-imaging Technology and Microvias in LTCC for Enhanced High-frequency Applications and Packaging Fraunhofer IKTS, Germany |
11:15am - 12:30pm | S 1C: Quality and Reliability Location: Mont Blanc |
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Study of a Failure of a Compact Ceramic No-lead Package Due to Tinning Induced Thermal Shock and Its Design Improvement 1Beijing Institute of Precision and Mechatronics and Controls; 2Laboratory of Aerospace Servo Actuation and Transmission Assessment of QFN Assemblies’ Thermal Strain Characterization and its Evolution Through Thermal Cycling Aging 1MBDA France, France; 2DGA MI, France; 3IMS Bordeaux, France Embedding of components as an effective way to achieve high reliability for special applications products Łukasiewicz Research Network - ITR, Poland |
11:15am - 12:30pm | S 1D: Assembly and Manufacturing Location: Makalu |
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Development of Advanced Screen-printing Technology for Flip-chip Transfer of Electronic Components CEA, France Thinning and Dicing Process Integration of High Accuracy Using A Novel Self-assembly Stage for Chip on Wafer LINTEC Corporation, Japan A Study of 355 nm UV Laser Ablation Process for Singulation of Silicon Wafers Microsys lab, Department of Electrical Engineering and Computer Science, University of Liège, Belgium |
12:30pm - 1:50pm | Lunch – Exhibition |
1:50pm - 3:05pm | S 2A: Interconnection Technologies Location: Amphitheatre |
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Characterization of Chip-to-wafer Interconnects with Thick Gold Finish for Fan-out Wafer-level Packaging RDL First Integration Univ. Grenoble Alpes, CEA, Leti, Grenoble, France Fine-pitch Die-to-wafer Bonding Technologies for Chiplet Integration 1All Silicon System Integration Dresden, Fraunhofer Institute for Reliability and Microintegration IZM, Dresden, Germany; 2Institute of Electronic Packaging Technology, Technische Universität Dresden, Dresden, Germany; 3Institutsteil Entwicklung Adaptiver Systeme EAS, Fraunhofer-Institut für Integrierte Schaltungen IIS, Dresden, Germany; 4Nanowired GmbH, Emanuel-Merck-Straße 99, Gernsheim, Germany Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die Commissariat à l'énergie atomique (CEA), France |
1:50pm - 3:05pm | S 2B: Design, Modelling and Simulation Location: Kilimandjaro |
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A Methodology for Modeling Capillary Underfill (CUF) in Advanced Packaging 1Henkel, United States of America; 2Henkel AG & Co. KGaA; 3Henkel Asia Pacific Simulation-based Analysis of Thermal Effects Induced by RF Interference in MEMS Microphones 1Rosenheim University of Applied Sciences, Rosenheim, Germany; 2Munich University of Applied Sciences, Munich, Germany; 3TDK Electronics AG, Munich, Germany Numerical Case Study of Stress and Plastic Strain Distributions in BGA Solder Balls by Comparison of a Novel Inorganic Encapsulation and Conventional Underfill Variants Fraunhofer Institute for Microstructure of Materials and Systems IMWS, Halle (Saale), Germany |
1:50pm - 3:05pm | S 2C: System in Package Location: Mont Blanc |
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Research on Damage Behaviour of Vertical Interconnection Solder Joints in a RF SiP Module China Electronic Product Reliability and Environmental Testing Research Institute, China, People's Republic of A Miniaturized Dual Band (28/39 GHz) AiP Design for Millimeter-Wave 5G Mobile Phone Applications Advanced Semiconductor Engineering, Inc.(ASE group), Taiwan Development of a 3D Quilt Packaging Method for Implantable Applications 1Imperial College London, United Kingdom; 2Mint Neurotechnologies Ltd |
1:50pm - 3:05pm | S 2D: Materials Location: Makalu |
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Bi–in Segregation in Low-temperature SLID Bonding: Au-in-bi System University of South Eastern Norway, Norway Large Area (> 2500mm²) Sintering at Sub 220°C With Micro-scale Copper Flakes 1CuNex GmbH, Ingolstadt, Germany; 2Technische Universität Berlin, Berlin, Germany Influence of Total Encapsulation of White-light Mid-power LED Packages Over the Correlated Colour Temperature THD Technologie Campus Cham, Germany |
3:05pm - 3:40pm | Break – Exhibition |
3:40pm - 4:25pm | Keynote 3 Location: Amphitheatre "Mass Transfer: How the Push for MicroLED Displays Opens New Paths to Heterogeneous Integration" by Dr. Chris Bower (CTO and co-founder, X Display Company (XDC)., Inc.) |
4:25pm - 4:35pm | Room Change |
4:35pm - 5:50pm | S 3A: Materials Location: Amphitheatre |
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Exploration of Cu Interfacial Engineering to Enhance Cu Interconnects Reliability University of North Texas, United States of America Tailored Polymers for Wafer-level Optics Manufacturing via Nanoimprint Lithography DELO Industrial Adhesives, Germany Evaluations of Transient Liquid Phase Joints Using In-coated Ag Sheet Osaka University, Japan |
4:35pm - 5:50pm | S 3B: Power Electronics Location: Kilimandjaro |
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Promoting EMC Adhesion to Copper Leadframe Through Oxide Thickness Optimization 1Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France; 2Valeo, Créteil, France; 3Valeo, Sable sur Sarthe, France Thermal and Structural Analysis of GaN Layers on Foreign Substrates for Vertical Power Devices 1Materials Center Leoben Forschung GmbH, Austria; 2Ferdinand-Braun-Institut, Germany The next generation die top system (Ag-only DTS®) for Cu wire bonding on SiC chips Heraeus Electronics GmbH & Co KG, Germany |
4:35pm - 5:50pm | S 3C: Qulaity and Reliability Location: Mont Blanc |
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The Effect of Solder Die Attach Voids on the Junction-to-case Thermal Resistance of MOSFET Packages CEPREI Laboratory, China, People's Republic of Experimental and Numerical Investigation of the Impact of Surface Roughness of Copper Plated through Holes on Thermomechanical Reliability 1Technische Universität Berlin, Germany; 2Fraunhofer IZM Berlin, Germany The Impact of Processing Conditions on Bond Reliability in Pressureless Silver Sintering Hitachi Energy Ltd., Switzerland |
4:35pm - 5:50pm | S 3D: Assembly and Manufactuirng Location: Makalu |
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A New Carrier Tape for Direct Transfer Bonding (DTB) Process with Ultra-thin Chips 1LINTEC Corporation, Japan; 2TAZMO CO.,LTD., Japan Ultra-precise Dispensing for High-resolution Redistribution Layers and 3D Interconnects in Advanced Packaging Applications XTPL SA, Poland Plasma Influence for Polymer Uniform Spreading on Heterogeneous Surfaces ST Microelectronis, France |
6:00pm - 7:30pm | Dinner: Tasting of regional products & Exhibitors' time (TBC) |
Date: Wednesday, 17/Sept/2025 | |
9:00am - 9:45am | Keynote 4 Location: Amphitheatre "Recent Trends in Automotive Power Module Designs and Technology for Traction Inverters" by Dr. Uwe Hansen (VP Power Component Development, Bosch) |
9:45am - 10:30am | Keynote 5 Location: Amphitheatre "System Technology Co-optimization for Advanced 3D & Heterogeneous Integration" by Sébastien Dauvé (CEO, CEA-Leti) |
10:30am - 11:15am | Break – Posters – Exhibition |
11:15am - 12:30pm | S 4A: Assembly and Manufacturing Location: Amphitheatre |
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In-situ Plasma Monitoring Study for Wire Bonding Process Improvements ST Microelectronis, France Impact and Control of Residual Stress in Ceramic Packages 1ASML Berlin, Germany; 2FAU Erlangen; 3Helmholtz-Zentrum Berlin Wafer dicing technique for close-butted assemblies CEA Grenoble, France |
11:15am - 12:30pm | S 4B: Design, Modelling and Simulation Location: Kilimandjaro |
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Intelligent Prediction of Warpage in Molded fcBGA Packages: An Optimization and Modeling Approach Advanced Semiconductor Engineering, Inc., Taiwan Comparative FEA Analysis of Cu Clip and Al Wire Bonding in Power Discrete Packages Dong-Eui University, Korea, Republic of (South Korea) Investigation of thermal performance of various thermal interface materials used in top-side-cooled MOSFETs 1Fraunhofer Institute for Electronic Nano Systems, Germany; 2Ideas & Motion s.r.l, Cherasco, Italy |
11:15am - 12:30pm | S 4C: IC Packagimg Location: Mont Blanc |
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Impact of PFAS Removal on the Harsh Environment Reliability of Semiconductor Packaging Auburn University, United States of America FC-LGA for Power Devices: Peculiarities and Challenges Compared with Digital Products STMicroelectronics Modular Integration of Sensor-Chiplets using Rapid Prototyping including Interconnects and Protective Waveguide Packaging Fraunhofer Institute for Photonic Microsystems – IPMS, Germany |
11:15am - 12:30pm | S 4D: POSTER SESSION #1 Location: Makalu |
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Thermomechanical Study for Stress-management of Silicon Photonics Interposers Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France Study on the Influence of Reflow Soldering on the Reliability of Mixed Solder Joints China CEPREI Laboratory, China, People's Republic of Reusing SMD Components on E-textiles: An Ageing Study by Combination of Corrosive Gases and Washing University of West Bohemia, Faculty of Electrical Engineering, Czech Republic A Comparative Study of Silver Sintering Pastes for Die-attach Applications: Microstructure, Mechanical Properties, and Reliability University of West Bohemia, Czech Republic Design and Evaluation of a Perforated Dielectric Flat Lens Antenna Array for D-band Applications Advanced Semiconductor Engineering, Inc., Taiwan A High Gain Antenna-in-Package (AiP) with Horn Structure for D-band Applications Advanced Semiconductor Engineering, Inc. (ASE), Taiwan Fine-pitch Flip-chip Bonding Process with Laser Non-conductive Paste (NCP) and Laser-assisted Bonding (LAB) for High-reliability ETRI, Korea, Republic of (South Korea) Electrochemical Analysis Reveals Effective Grain Refinement in Copper Electroplating Advanced Semiconductor Engineering, Inc., Taiwan Indium as the Superconducting Interconnect for Quantum Chiplets 1Institute of Advanced Sciences, Yokohama National University, Japan; 2Graduate School of Engineering, Yokohama National University, Japan; 3Faculty of Engineering, Yokohama National University, Japan Test Equipment for Sensor Interfaces Emulated by Generic Electronic Control Unit National University of Sciences and Technologies Politehnica, Bucharest, Romania Visualizing Vibrations of Electronic Modules in Test Landshut University of Applied Sciences, Germany Grain Orientation Analysis for Thermal Cycling Evaluation of Die-attach Solder Joints 1The University of Osaka, Japan; 2RIKEN SPring-8 Center, Japan; 3Japan Synchrotron Radiation Research Institute, Japan Thermal Fatigue Resistance Improvement of New Al Bonding Wire 1Nippon Micrometal Corporation, Japan; 2Fraunhofer-Institute for Microstructure of Materials and Systems IMWS; 3Nippon Steel Corporation Thermal Analysis of Power Electronic Modules with Parametric Model Order Reduction 1School of Computing and Mathematical Sciences, University of Greenwich, London, United Kingdom; 2Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham, United Kingdom |
12:30pm - 1:50pm | Lunch Break – Posters – Exhibition |
1:50pm - 3:30pm | S 5A: Substrate Technologies Location: Amphitheatre |
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Approach for Extracting the Relative Permittivity of Sol-gel Using a Ring Resonator Fabricated on an LTCC Substrate 1IMT atlantique, France; 2Technische Universität Ilmenau Insulation Layers on Copper Surfaces of Ceramic Circuit Boards for Smart Power Modules Fraunhofer Institute for Ceramic Technologies and Systems IKTS, Germany Optimized Castellated Hole Interconnects for Ceramic-based Modular Millimeter-Wave Applications up to 85 GHz 1Fraunhofer IZM, Germany; 2VIA electronic GmbH, Germany Glasses as substrates for packaging: Remarks on mechanic reliability. 1SCHOTT AG, Mainz, Germany; 2SCHOTT Semicon Glass Solutions, Mainz, Germany |
1:50pm - 3:30pm | S 5B: Optoelectronics Location: Kilimandjaro |
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Precise Alignment and Laser-assisted Bonding of Multichannel Laser Diode Chips for Silicon Photonics Integration Optoelectronics Research Centre, ENS Faculty, Tampere University, Finland Assembly Perspectives on Flip-chip Integration of 1x, 4x and 8x Array InP-SiN Hybrid Laser Devices to Si Photonics Wafers with Sub-500 nm Misalignment 1imec, Belgium; 2ASMPT, Germany; 3Sivers Photonics, Scotland TSVs Mechanical Stress Measurements on Silicon Wave-guide Using Phase Shift Interferometry 1Univ. Grenoble Alpes, CEA, Leti, Grenoble, France; 2STMicroelectronics Crolles, France Package and Process Development of Molded Image Sensor Package UTAC Group, Singapore |
1:50pm - 3:30pm | S 5C: Emerging Technologies Location: Mont Blanc |
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TBM-free Plasma Etch Die Singulation HRL Laboratories, United States of America Anti-counterfeit Semiconductor Package Using a Unique Identification Mark 1LINTEC corporation; 2Yokohama National University; 3National Institute of Advanced Industrial Science and Technology Metal Oxide Reduction Using Inline Openair-plasma Process to Enhance Adhesion and Improve Durability in Electronics 1Plasmatreat GmbH, Steinhagen, Germany; 2Plasmatreat USA, Haward, USA Surface Conditioning of LTCC Substrates for Improved RF Signal Propagation 1TU Ilmenau, Germany; 2Institut Mines-Télécom, France |
1:50pm - 3:30pm | S 5D: POSTER SESSION #2 Location: Makalu |
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Microelectronic Packaging Challenges for Stacked Superconducting Qubit Chips Using Indium Bump Bonding 1Technology, STFC-RAL, United Kingdom; 2National Quantum Computing Centre (NQCC), STFC, United Kingdom; 3Central Laser Facility (CLF), STFC-RAL, United Kingdom Flip-chip Bonded Hybrid Germanium X-ray Detectors Suitable for Operating with Thermal Gradient Between Sensor and ASIC 1STFC-RAL, United Kingdom; 2STFC-DL, United Kingdom Thermal Management of an Electronic Module Made by a Solderless Assembly Method 1Syswin Solutions, Romania; 2Electronic Technology & Reliability Department, National University of Science and Technology Politehnica Bucharest, Romania; 3Department of Metallic Materials Sciences, Physical Metallurgy, Faculty of Materials Science and Engineering, National University of Science and Technology Politehnica Bucharest, Romania Selective Micro Laser Melting: Influence of Scan Speed and Laser Power on Interconnect Morphology and Performance Indian Institute of Science, Bengaluru, India Flip Chip Bonding of PMUT Using Adhesives and their Effect on Electrical Performance Silicon Austria Labs, Automated Non-destructive Mechanical Testing of Fine Pitch Wirebond Arrays Sandia National Laboratories, United States of America Advanced Underfill Developments Enabling Complex AI and HPC Package Designs Henkel Nederland BV, Netherlands, The Advanced Dielectric Films for Fusion Bonded 3D Integration Yokohama National University, Japan Printable non-volatile and volatile memristors based on Lead-Free Perovskites for artificial synapses and neurons emulation Hellenic Mediterranean University, Greece Power modules: Crack and shrinkage phenomenon PROTAVIC, France Void inspection using stress field imaging in densely patterned bonded wafers Semilab Co. Ltd., Hungary Photoresist/polymer removal optimized chemistry with adding hydrogen radical in MEMS process fabrication and other applications with HDRF® Plasma-Therm Europe, France Innovative deposition solution for TSV integration and conformal deposition of oxide, nitride, and metal layer with dual frequency pulsed equipment, application of low temperature deposition of dielectric layer Plasma-Therm Europe, France Temperature Profile Optimization for Vacuum Soldering of Components on Heat Sink 1University of West Bohemia, Czech Republic; 2Rohde & Schwarz závod Vimperk, s.r.o., Czech Republic Investigating the Dynamic Bending Behaviour of Biodegradable Printed Circuit Boards Budapest University of Technology and Economics, Hungary Stacked and Staggered Vias in FR4 laminate for special application Łukasiewicz Research Network - ITR, Poland Engineering Dual Alloy Solder Paste Systems to Achieve High Reliability, Energy Savings, Withstand High Junction Temperatures Indium Corporation Warpage Reduction of Laminate Substrates Through Metamodel-based Optimization of Material Properties 1CSA R&D ET Packaging Development, Materials and Simulation- ams OSRAM AG, Premstaetten, Austria; 2Institute of Materials Science and Testing of Polymers- Montanuniversität Leoben, Leoben, Austria; 3Simulation and Modeling- Polymer Competence Centre Leoben (PCCL) GmbH, Leoben, Austria; 4Surface Testing, Robot Vision and Artificial Intelligence- Polymer Competence Centre Leoben (PCCL) GmbH, Leoben, Austria |
3:30pm - 4:05pm | Break – Posters – Exhibition |
4:05pm - 5:20pm | S 6A: System in Package Location: Amphitheatre |
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Highly Integrated Low Power Wireless Sensor Node 1STMicroelectronics, Italy; 2Scuola Superiore Sant'Anna, Italy; 3CamGraPhIC, Italy Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration Univ. Grenoble Alpes, CEA, Leti RF Characterization of Microscale Transmission Lines on Polymer-based Silicon Interposers for HPC Applications 1Fraunhofer IZM, Germany; 2Brandenburg University of Technology (BTU) Cottbus-Senftenberg, Cottbus, Germany |
4:05pm - 5:20pm | S 6B: Quality and Reliability Location: Kilimandjaro |
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Advanced Defects Repair Techniques for Enhancing Yield in Packaging Architectures KLA, Israel Prognostics and Health Monitoring: Case Study of a Light Rail Vehicle Power Converter Assembly Fraunhofer Institute for Ceramic Technologies and Systems IKTS, Germany Optimizing Ag Paste Thickness for Reliable Power Module Packaging 1Osaka University, Japan; 2Daicel Corporation, Japan |
4:05pm - 5:20pm | S 6C: Materials Location: Mont Blanc |
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Ag-nodule Mediated Bonding Using Liquid Quenched Ag-Si Alloy 1Osaka University, Japan; 2Daicel Corporation, Japan Thermal Characterization of Electrically Conductive Adhesives and Pressureless Sinter Pastes – Comparison of Data Sheet and Real Application 1Baker Hughes Inteq GmbH, Germany; 2Novicos GmbH; 3Faculty of Electrical Engineering and Information Technology, Technical University Chemnitz Characterisation and Modelling of Sintered Joints Used in Power Electronics Valeo, France |
5:45pm | Bus transfer: Busses leaving venue for confernce dinner |
7:00pm - 10:00pm | Conference Dinner |
Date: Thursday, 18/Sept/2025 | |
8:45am - 9:30am | Keynote 6 Location: Amphitheatre "Advanced Packaging – The Key Technology for Chiplet Integration" by Prof. Dr.-Ing. Ulrike Ganesh (Managing Director, Fraunhofer IZM) |
9:30am - 9:40am | Room Change |
9:40am - 10:55am | S 7A: Smart Manufacturing Location: Amphitheatre |
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Process Development for Cu Metallization on SiC MOSFETs with Inkjet Printing Technology 1Robert Bosch GmbH, Germany; 2University of Stuttgart Development of a Novel Pure-ag-sintering Paste for a Jet-dispensing Process to Achieve Highest Possible Conductivity for Miniaturized Electronic Components with a Pressure-less Sintering Process Nano-Join GmbH, Germany Additive Manufacturing of High-Performance Ceramics for Fabricating Single- and Multi-Material Components 1Lithoz GmbH, Austria; 2Montanuniversitaet Leoben, Austria |
9:40am - 10:55am | S 7B: IC Packaging Location: Kilimandjaro |
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"Advanced Packaging" — A must for the Next-Gen AI and HPC Hardware ! And not Only ! Yole Group, France Advancing IC Substrate Manufacturing: Overcoming Challenges and Exploring Opportunities with 10µm Line/Space Technology GS Swiss PCB AG, Switzerland Heterogeneous Integration and Wafer-level Packaging by Micro-transfer-printing X-FAB MEMS Foundry GmbH, Germany |
9:40am - 10:55am | S 7C: Intreconnection Technologies Location: Mont Blanc |
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A Novel Photo-patternable Epoxy Flux Material for A New Horizon in Fine Pitch Flip-chip Interconnections 1Electronics and Telecommunications Research Institute, Korea, Republic of (South Korea); 2Pusan National University, Korea, Republic of (South Korea) Femtosecond Laser Drilling Technologies for Through Glass Via (TGV) Fabrication in Customised Glass Interposers Oxford Lasers Ltd, United Kingdom Integration Technology Development of Chip-Antenna Interface for Short Range mmWave Wireless Communication 1Institute of Electronic Packaging Technology, Technische Universität Dresden, Germany; 2Chair for Circuit Design and Network Theory, Technische Universität Dresden, Germany; 3Chair for RF and Photonics Engineering, Technische Universität Dresden, Germany |
9:40am - 10:55am | S 7D: Inspection and Test Location: Makalu |
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Key Technologies and Design Aspects for Advanced FOCoS Packaging Advanced Semiconductor Engineering, Taiwan Lensless Through-silicon Microscopy System for Precise Alignment in Photonic Integration Processes 1Optoelectronic Research Centre, ENS Faculty, Tampere University, Finland; 2Computational Imaging Group, ITC Faculty, Tampere University, FInland; 3Photonics Group, Tampere University, FInland; 4Ampliconyx Oy, Finland; 5TU Ilmenau, Germany Investigating the Role of Thermal Effects in RF Immunity of MEMS Microphones 1Department of Electrical Engineering, Munich University of Applied Sciences, Munich, Germany; 2TDK Electronics AG, Munich, Germany; 3Centre for Research and Development, Rosenheim University of Applied Sciences, Rosenheim, Germany; 4TDK InvenSense, Boston, USA |
10:55am - 11:30am | Break – Exhibition |
11:30am - 12:45pm | S 8A: Quality and Reliability Location: Amphitheatre |
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Defining a Scalable Test Methodology to Deliver High Quality AI Products Meta Platforms Inc., United States of America Microstructural Characterization for the Joining Interface of Ag@Si Composite Sinter Joining for SiC Power Device by Scanning Transmission Electron Microscopy 1F3D system Integration Lab, SANKEN, Osaka University, Japan; 2Daicel Corporation SACN doped solder balls alloys aging impact on BGA's reliability performance STMicroelectronics, France |
11:30am - 12:45pm | S 8B: Assembly and Manufcaturing Location: Kilimandjaro |
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High density 3D interconnections for high performance CdTe based X-rays detectors 13D PLUS, France; 2Université Paris-Saclay, Université Paris Cité, CEA, CNRS, AIM; 3IRFU, CEA, Université Paris-Saclay Atmospheric Plasma Cleaning of Copper Oxide and Tin Oxide for Flux-Free Interconnect Bonding Ontos Equipment Systems (OES), United States of America A single step process for Die-attach and substrate-attach with pressure assisted sintering to face harsh conditions 1Inventec Preformance Chemicals, France; 2NANO-JOIN |
11:30am - 12:45pm | S 8C: Power Electronics Location: Mont Blanc |
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Measurements at High Temperature for Thermal Resistance of MOSFETs National University of Science and Technology POLITEHNICA Bucharest, Romania Influence of Uneven Chip Solder Layer Thickness on the Reliability of Power Modules Siemens AG, Germany Reliability Evaluation of Direct Bonding for SiC Power Devices by Power Cycling Test 1Hamm-Lippstadt University of Applied Sciences, Germany; 2Semikron Danfoss Elektronik GmbH & Co. KG, Nuremberg, Germany |
11:30am - 12:45pm | S 8D: Materials Location: Makalu |
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Understanding Solder Creepage in Thin Si Devices Through Advanced Traceability Systems 1STMicroelectronics, Morocco; 2STMicroelectronics, France Enhancing the Reliability of Harsh Environment Electronics Through PFAS-free Multilayer ALD + Parylene Coatings Specialty Coating Systems, Inc., United States of America Insulation Materials for Advanced Packaging Applications Ajinomoto Co., Inc., Japan |
12:45pm - 2:00pm | Lunch – Exhibition |
2:00pm - 2:45pm | Keynote 7 Location: Amphitheatre "Charting a Path for the Chiplet Era and Beyond" by Craig Bishop (Chief Technology Officer, Deca Technologies) |
2:45pm - 3:15pm | Awards and Closing Location: Amphitheatre |
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