The 25th European Microelectronics &
Packaging Conference (EMPC 2025)
16 – 18 September 2025
World Trade Center, Grenoble | France
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview | |
Location: Kilimandjaro |
Date: Monday, 15/Sept/2025 | |
9:00am - 1:00pm |
SC 2: Short Course Location: Kilimandjaro "Microelectronics Packaging Basics in Practice!" Short Course Instructor: Valérie Volant, STMicroelectronics |
2:00pm - 6:00pm |
SC 4: Short Course Location: Kilimandjaro "Electronic/Photonic Convergence Using Advanced Packaging: A Status" Short Course Instructor: Stéphane Bernabé, CEA LETI |
Date: Tuesday, 16/Sept/2025 | |
11:15am - 12:30pm |
S 1B: Interconnection Technologies Location: Kilimandjaro Material Challenges for Fine Interconnection in Advanced Packages Stability of the Superconducting β-Sn Phase at Low Temperatures for 3D Cryogenic Packaging Integration of Photo-imaging Technology and Microvias in LTCC for Enhanced High-frequency Applications and Packaging |
1:50pm - 3:05pm |
S 2B: Interconnection Technologies Location: Kilimandjaro Characterization of Chip-to-wafer Interconnects with Thick Gold Finish for Fan-out Wafer-level Packaging RDL First Integration Fine-pitch Die-to-wafer Bonding Technologies for Chiplet Integration Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die |
4:35pm - 5:50pm |
S 3B: Power Electronics Location: Kilimandjaro Promoting EMC Adhesion to Copper Leadframe Through Oxide Thickness Optimization Correlated Thermal and Structural Characterization of GaN on Sapphire for Vertical Power Devices: Strain, Lattice Parameters, and Phonon Scattering Analysis The next generation die top system (Ag-only DTS®) for Cu wire bonding on SiC chips |
Date: Wednesday, 17/Sept/2025 | |
11:00am - 12:15pm |
S 4B: Design, Modelling and Simulation Location: Kilimandjaro Intelligent Prediction of Warpage in Molded fcBGA Packages: An Optimization and Modeling Approach Comparative FEA Analysis of Cu Clip and Al Wire Bonding in Power Discrete Packages Investigation of thermal performance of various thermal interface materials used in top-side-cooled MOSFETs |
1:35pm - 3:15pm |
S 5B: Optoelectronics Location: Kilimandjaro Precise Alignment and Laser-assisted Bonding of Multichannel Laser Diode Chips for Silicon Photonics Integration Assembly Perspectives on Flip-chip Integration of 1x, 4x and 8x Array InP-SiN Hybrid Laser Devices to Si Photonics Wafers with Sub-500 nm Misalignment Impact of TSV Mechanical Stress on Silicon Wave-guides Using Phase Shift Interferometry Package and Process Development of Molded Image Sensor Package |
3:50pm - 5:05pm |
S 6B: Quality and Reliability Location: Kilimandjaro Advanced Techniques for Short Defect Repair to Improve Yield in Packaging Architectures Prognostics and Health Monitoring: Case Study of a Light Rail Vehicle Power Converter Assembly Optimizing Ag Paste Thickness for Reliable Power Module Packaging |
Date: Thursday, 18/Sept/2025 | |
9:40am - 10:55am |
S 7B: IC Packaging Location: Kilimandjaro "Advanced Packaging" — A must for the Next-Gen AI and HPC Hardware ! And not Only ! Advancing IC Substrate Manufacturing: Overcoming Challenges and Exploring Opportunities with 10µm Line/Space Technology Heterogeneous Integration and Wafer-level Packaging by Micro-transfer-printing |
11:30am - 12:45pm |
S 8B: Assembly and Manufacturing Location: Kilimandjaro High density 3D interconnections for high performance CdTe based X-rays detectors Atmospheric Plasma Cleaning of Copper Oxide and Tin Oxide for Flux-Free Interconnect Bonding A single step process for Die-attach and substrate-attach with pressure assisted sintering to face harsh conditions |