Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
Only Sessions at Location/Venue 
 
 
Session Overview
Location: Amphitheatre
Date: Tuesday, 16/Sept/2025
9:10am
-
9:55am
Keynote 1
Location: Amphitheatre

"Propelling AI forward through Advanced Packaging Creativity"
by Ingu Yin Chang (Executive Vice President, ASE Inc.)

9:55am
-
10:40am
Keynote 2
Location: Amphitheatre

"The Interconnect 'Panelization'"
by Laurent Herard (Group VP – Head of Back End Manufacturing & Technology R&D, STMicroelectronics)

11:15am
-
12:30pm
S 1A: IC Packaging
Location: Amphitheatre
 

Development of Die Attach Process for Thin Device Using a Novel High Thermal Conductivity Pressure-less Semi-sintering Paste with Capillary Filling Technology

Shogo Nakano, Low Shuey Seng, Nicoletta Modarelli, Matteo Luca Quattrocchio



A Novel Package Technology for Better MOSFET Performance

Arnel Taduran, Ilyas Dchar, Ding Yandoc



Fan Out Wafer Level Packaging – Towards a European Manufacturing Supply Chain

Marc Dreissigacker, Daniel Lieske, Tanja Braun, Markus Wöhrmann

1:50pm
-
3:05pm
S 2A: Interconnection Technologies
Location: Amphitheatre
 

Characterization of Chip-to-wafer Interconnects with Thick Gold Finish for Fan-out Wafer-level Packaging RDL First Integration

Arnaud Garnier, Laetitia Castagné, Guenaëlle Massignac, Rémi Franiatte, Daniel Mermin, Alain Gueugnot, Perceval Coudrain



Fine-pitch Die-to-wafer Bonding Technologies for Chiplet Integration

Juliana Panchenko, Laura Wenzel, Steffen Bickel, Adil Shehzad, Fabian Hopsch, Sebastian Quednau, Manuela Junghaehnel



Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die

Mel Dehays, Sébastien Renet, Olivier Mailliart, Patrick Peray, Frédéric Berger, Guillaume Lamarache

3:40pm
-
4:25pm
Keynote 3
Location: Amphitheatre

"Mass Transfer: How the Push for MicroLED Displays Opens New Paths to Heterogeneous Integration"
by Dr. Chris Bower (CTO and co-founder, X Display Company (XDC)., Inc.)

4:35pm
-
5:50pm
S 3A: Materials
Location: Amphitheatre
 

Exploration of Cu Interfacial Engineering to Enhance Cu Interconnects Reliability

Kevin Antony Jesu Durai, Dinesh Kumar Kumaravel, Shyam Muralidharan Nair, Khanh Tran, Shinoj Sridharan Nair, Oliver Chyan



Tailored Polymers for Wafer-level Optics Manufacturing via Nanoimprint Lithography

Patrick Schirmer, Heinrich Trischler, Stephan Prinz



Evaluations of Transient Liquid Phase Joints Using In-coated Ag Sheet

Xunda Liu, Hiroaki Tatsumi, Zhi Jin, Hiroshi Nishikawa

Date: Wednesday, 17/Sept/2025
9:00am
-
9:45am
Keynote 4
Location: Amphitheatre

"Recent Trends in Automotive Power Module Designs and Technology for Traction Inverters"
by Dr. Uwe Hansen (VP Power Component Development, Bosch)

9:45am
-
10:30am
Keynote 5
Location: Amphitheatre

"System Technology Co-optimization for Advanced 3D & Heterogeneous Integration"
by Sébastien Dauvé (CEO, CEA-Leti)

11:15am
-
12:30pm
S 4A: Assembly and Manufacturing
Location: Amphitheatre
 

In-situ Plasma Monitoring Study for Wire Bonding Process Improvements

Nohora Caicedo, Patricia Folio, Valentin Ray, Laurence Capellaro, Justin Catania



Impact and Control of Residual Stress in Ceramic Packages

Markus Eberstein, William Kuhblank, Rita Cicconi, Dominique de Ligny, Daniel Apel, Mirko Boin



Wafer dicing technique for close-butted assemblies

Sarah Renault, Aurélia Plihon, Emerick Lorent, Myriam Tournaire, Nicolas Bresson, Delphine Rolland

1:50pm
-
3:30pm
S 5A: Substrate Technologies
Location: Amphitheatre
 

Approach for Extracting the Relative Permittivity of Sol-gel Using a Ring Resonator Fabricated on an LTCC Substrate

Achraf Sadeddine, Norayr Nessimian, Camilla Karnfelt, Heike Bartsch, Jens Mueller



Insulation Layers on Copper Surfaces of Ceramic Circuit Boards for Smart Power Modules

Claudia Feller, Henry Barth, Stefan Körner, Lars Rebenklau



Optimized Castellated Hole Interconnects for Ceramic-based Modular Millimeter-Wave Applications up to 85 GHz

Paul Perlwitz, Christian Tschoban, Uwe Krieger, Qaisar Khushi Muhammad, Harald Pötter, Martin Schneider-Ramelow



Glasses as substrates for packaging: Remarks on mechanic reliability.

Martin Letz, Fabian Wagner, Inge Burger, Rule Kirchhoff, Volker Seibert, Ulrich Peuchert

4:05pm
-
5:20pm
S 6A: System in Package
Location: Amphitheatre
 

Highly Integrated Low Power Wireless Sensor Node

Luca Maggi, Marco Del Sarto, Amedeo Maierna, Alex Gritti, Claudio Porzi, Gaspare Santaera, Filippo Scotti, Marc Sorel, Cesare Stefanini, Antonella Bogoni, Piero Castoldi, Marco Chiesa, Aina Serrano Rodrigo, Davide Rotta



Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration

Perceval Coudrain, Laetitia Castagné, Arnaud Garnier, Raphaël Eleouet, Emmeline Tomas, Rémi Franiatte, Rémi Vélard, Nadia Miloud-Ali, Thierry Mourier



RF Characterization of Microscale Transmission Lines on Polymer-based Silicon Interposers for HPC Applications

Alexander Gaebler, Uwe Maaß, Ivan Ndip, Kai Zoschke, Marius Adler

Date: Thursday, 18/Sept/2025
8:45am
-
9:30am
Keynote 6
Location: Amphitheatre

"Advanced Packaging – The Key Technology for Chiplet Integration"
by Prof. Dr.-Ing. Ulrike Ganesh (Managing Director, Fraunhofer IZM)

9:40am
-
10:55am
S 7A: Smart Manufacturing
Location: Amphitheatre
 

Process Development for Cu Metallization on SiC MOSFETs with Inkjet Printing Technology

Xiaojie Tian, Golzar Alavi, Bernhard Polzinger, André Zimmermann



Development of a Novel Pure-ag-sintering Paste for a Jet-dispensing Process to Achieve Highest Possible Conductivity for Miniaturized Electronic Components with a Pressure-less Sintering Process

Battist Rábay, Adrian Stelzer, Julien Hossain



Additive Manufacturing of High-Performance Ceramics for Fabricating Single- and Multi-Material Components

Martin Schwentenwein, Josef Schlacher, Serkan Nohut, Sebastian Geier, Raul Bermejo

11:30am
-
12:45pm
S 8A: Quality and Reliability
Location: Amphitheatre
 

Defining a Scalable Test Methodology to Deliver High Quality AI Products

Soumya Padmanabha, Gautam Nayak, Zhenxuan Zhang



Microstructural Characterization for the Joining Interface of Ag@Si Composite Sinter Joining for SiC Power Device by Scanning Transmission Electron Microscopy

Masahiko Nishijima, Ran Liu, Yang Liu, Koji. S Nakayama, Cuantong Chen, Minoru Ueshima, Katsuaki Suganuma



SACN doped solder balls alloys aging impact on BGA's reliability performance

Edwin Wakem Tangui, Laurence Capellaro, Nohora Caicedo

2:00pm
-
2:45pm
Keynote 7
Location: Amphitheatre

"Charting a Path for the Chiplet Era and Beyond"
by Craig Bishop (Chief Technology Officer, Deca Technologies)

2:45pm
-
3:15pm
Awards and Closing
Location: Amphitheatre

 
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