The 25th European Microelectronics &
Packaging Conference (EMPC 2025)
16 – 18 September 2025
World Trade Center, Grenoble | France
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview |
Date: Thursday, 18/Sept/2025 | ||||
8:45am - 9:30am |
Keynote 6 Location: Amphitheatre "Advanced Packaging – The Key Technology for Chiplet Integration" by Prof. Dr.-Ing. Ulrike Ganesh (Managing Director, Fraunhofer IZM) |
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9:30am - 9:40am |
Room Change |
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9:40am - 10:55am |
S 7A: Smart Manufacturing Location: Amphitheatre Process Development for Cu Metallization on SiC MOSFETs with Inkjet Printing Technology Development of a Novel Pure-ag-sintering Paste for a Jet-dispensing Process to Achieve Highest Possible Conductivity for Miniaturized Electronic Components with a Pressure-less Sintering Process Additive Manufacturing of High-Performance Ceramics for Fabricating Single- and Multi-Material Components |
S 7B: IC Packaging Location: Kilimandjaro "Advanced Packaging" — A must for the Next-Gen AI and HPC Hardware ! And not Only ! Advancing IC Substrate Manufacturing: Overcoming Challenges and Exploring Opportunities with 10µm Line/Space Technology Heterogeneous Integration and Wafer-level Packaging by Micro-transfer-printing |
S 7C: Intreconnection Technologies Location: Mont Blanc A Novel Photo-patternable Epoxy Flux Material for A New Horizon in Fine Pitch Flip-chip Interconnections Femtosecond Laser Drilling Technologies for Through Glass Via (TGV) Fabrication in Customised Glass Interposers Integration Technology Development of Chip-Antenna Interface for Short Range mmWave Wireless Communication |
S 7D: Inspection and Test Location: Makalu Key Technologies and Design Aspects for Advanced FOCoS Packaging Lensless Through-silicon Microscopy System for Precise Alignment in Photonic Integration Processes Investigating the Role of Thermal Effects in RF Immunity of MEMS Microphones |
10:55am - 11:30am |
Break – Exhibition |
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11:30am - 12:45pm |
S 8A: Quality and Reliability Location: Amphitheatre Defining a Scalable Test Methodology to Deliver High Quality AI Products Microstructural Characterization for the Joining Interface of Ag@Si Composite Sinter Joining for SiC Power Device by Scanning Transmission Electron Microscopy SACN doped solder balls alloys aging impact on BGA's reliability performance |
S 8B: Assembly and Manufcaturing Location: Kilimandjaro High density 3D interconnections for high performance CdTe based X-rays detectors Atmospheric Plasma Cleaning of Copper Oxide and Tin Oxide for Flux-Free Interconnect Bonding A single step process for Die-attach and substrate-attach with pressure assisted sintering to face harsh conditions |
S 8C: Power Electronics Location: Mont Blanc Measurements at High Temperature for Thermal Resistance of MOSFETs Influence of Uneven Chip Solder Layer Thickness on the Reliability of Power Modules Reliability Evaluation of Direct Bonding for SiC Power Devices by Power Cycling Test |
S 8D: Materials Location: Makalu Understanding Solder Creepage in Thin Si Devices Through Advanced Traceability Systems Enhancing the Reliability of Harsh Environment Electronics Through PFAS-free Multilayer ALD + Parylene Coatings Insulation Materials for Advanced Packaging Applications |
12:45pm - 2:00pm |
Lunch – Exhibition |
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2:00pm - 2:45pm |
Keynote 7 Location: Amphitheatre "Charting a Path for the Chiplet Era and Beyond" by Craig Bishop (Chief Technology Officer, Deca Technologies) |
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2:45pm - 3:15pm |
Awards and Closing Location: Amphitheatre |
Contact and Legal Notice · Contact Address: Privacy Statement · Conference: EMPC 2025 |
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