The 25th European Microelectronics &
Packaging Conference (EMPC 2025)
16 – 18 September 2025
World Trade Center, Grenoble | France
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview |
Date: Tuesday, 16/Sept/2025 | ||||
9:00am - 9:10am |
Welcome & Conference Opening |
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9:10am - 9:55am |
Keynote 1 Location: Amphitheatre "Propelling AI forward through Advanced Packaging Creativity" by Ingu Yin Chang (Executive Vice President, ASE Inc.) |
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9:55am - 10:40am |
Keynote 2 Location: Amphitheatre "The Interconnect 'Panelization'" by Laurent Herard (Group VP – Head of Back End Manufacturing & Technology R&D, STMicroelectronics) |
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10:40am - 11:15am |
Break – Exhibition |
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11:15am - 12:30pm |
S 1A: IC Packaging Location: Amphitheatre Development of Die Attach Process for Thin Device Using a Novel High Thermal Conductivity Pressure-less Semi-sintering Paste with Capillary Filling Technology A Novel Package Technology for Better MOSFET Performance Fan Out Wafer Level Packaging – Towards a European Manufacturing Supply Chain |
S 1B: Intreconnection Technologies Location: Kilimandjaro Material Strategy and Challenges for Fine Interconnection in Advanced Packages Stability of the Superconducting β-Sn Phase at Low Temperatures for 3D Cryogenic Packaging Integration of Photo-imaging Technology and Microvias in LTCC for Enhanced High-frequency Applications and Packaging |
S 1C: Quality and Reliability Location: Mont Blanc Defining a Scalable Test Methodology to Deliver High Quality AI Products Embedding of components as an effective way to achieve high reliability for special applications products Assessment of QFN Assemblies’ Thermal Strain Characterization and its Evolution Through Thermal Cycling Aging |
S 1D: Assembly and Manufacturing Location: Makalu Development of Advanced Screen-printing Technology for Flip-chip Transfer of Electronic Components Thinning and Dicing Process Integration of High Accuracy Using A Novel Self-assembly Stage for Chip on Wafer A Study of 355 nm UV Laser Ablation Process for Singulation of Silicon Wafers |
12:30pm - 1:50pm |
Lunch – Exhibition |
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1:50pm - 3:05pm |
S 2A: Design, Modelling and Simulation Location: Amphitheatre A Methodology for Modeling Capillary Underfill (CUF) in Advanced Packaging Simulation-based Analysis of Thermal Effects Induced by RF Interference in MEMS Microphones Numerical Case Study of Stress and Plastic Strain Distributions in BGA Solder Balls by Comparison of a Novel Inorganic Encapsulation and Conventional Underfill Variants |
S 2B: Interconnection Technologies Location: Kilimandjaro Characterization of Chip-to-wafer Interconnects with Thick Gold Finish for Fan-out Wafer-level Packaging RDL First Integration Fine-pitch Die-to-wafer Bonding Technologies for Chiplet Integration Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die |
S 2C: Special Topics Location: Mont Blanc Advanced Dielectric Films for Fusion Bonded 3D Integration A Miniaturized Dual Band (28/39 GHz) AiP Design for Millimeter-Wave 5G Mobile Phone Applications Development of a 3D Quilt Packaging Method for Implantable Applications |
S 2D: Materials Location: Makalu Bi–in Segregation in Low-temperature SLID Bonding: Au-in-bi System Large-area (> 1600 mm²) Sintering at 220°C with Micro-Scale Copper Flakes Influence of Total Encapsulation of White-light Mid-power LED Packages Over the Correlated Colour Temperature |
3:05pm - 3:40pm |
Break – Exhibition |
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3:40pm - 4:25pm |
Keynote 3 Location: Amphitheatre "Mass Transfer: How the Push for MicroLED Displays Opens New Paths to Heterogeneous Integration" by Dr. Chris Bower (CTO and co-founder, X Display Company (XDC)., Inc.) |
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4:25pm - 4:35pm |
Room Change |
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4:35pm - 5:50pm |
S 3A: Materials Location: Amphitheatre Exploration of Cu Interfacial Engineering to Enhance Cu Interconnects Reliability Tailored Polymers for Wafer-level Optics Manufacturing via Nanoimprint Lithography Evaluations of Transient Liquid Phase Joints Using In-coated Ag Sheet |
S 3B: Power Electronics Location: Kilimandjaro Promoting EMC Adhesion to Copper Leadframe Through Oxide Thickness Optimization Thermal and Structural Analysis of GaN Layers on Foreign Substrates for Vertical Power Devices The next generation die top system (Ag-only DTS®) for Cu wire bonding on SiC chips |
S 3C: Quality and Reliability Location: Mont Blanc Microstructural Characterization for the Joining Interface of Ag@Si Composite Sinter Joining for SiC Power Device by Scanning Transmission Electron Microscopy Experimental and Numerical Investigation of the Impact of Surface Roughness of Copper Plated through Holes on Thermomechanical Reliability The Impact of Processing Conditions on Bond Reliability in Pressureless Silver Sintering |
S 3D: Assembly and Manufacturing Location: Makalu A New Carrier Tape for Direct Transfer Bonding (DTB) Process with Ultra-thin Chips Ultra-precise Dispensing for High-resolution Redistribution Layers and 3D Interconnects in Advanced Packaging Applications Microelectronic Packaging Challenges for Stacked Superconducting Qubit Chips Using Indium Bump Bonding |
6:00pm - 7:30pm |
Dinner: Tasting of regional products & Exhibitors' time (TBC) |