Conference Agenda

Until now, system-level simulations that include electrostatic discharge (ESD) protection devices have relied on strong simplifications of the ESD device itself. For Signal Integrity (SI) simulations, high-speed engineers typically use simple capacitors or basic RLC circuits to introduce some level of realism. In ESD simulations, the industry has adopted the System Efficient ESD Design (SEED) methodology, which utilizes Transmission Line Pulsed (TLP) data to replicate the behavior of ESD devices under pulsed conditions. The simulation is then performed at the circuit level, incorporating simplifications and model reductions based on SPICE modeling.

In this workshop, we demonstrate how electronic components, including ESD devices, can be modeled as 3D structures. We will present a step-by-step process for developing these models, selecting and validating the electrical parameters of materials. Additionally, we will explore their application in SI simulations, showcasing results in both the frequency and time domains.

Building on this, we integrate these 3D models with the SEED methodology for ESD simulations. Finally, we discuss their impact at the system level, illustrating how these models enhance simulation accuracy—particularly in terms of S-parameters and ESD clamping behavior.