Conference Agenda

In recent years, power semiconductor technologies have made considerable progress with the result that a large number of different transistor technologies are available. Wide band gap semiconductors such as silicon-carbide (SiC) MOSFETs are preferred in power electronic applications due to lower switching losses compared to Si-MOSFETs and IGBTs. At lower voltages the gallium-nitrite (GaN) technology can reduce losses further. This makes modern power electronics application a potential source of electromagnetic interference (EMI). The half-bridge is a central circuit topology in most applications. In this paper, a half-bridge Buck-Converter is investigated and the switching signals are analyzed together with their resulting common mode (CM) EMI. Si, SiC and GaN transistor technologies are compared with each other under different operating points and the influence on the CM EMI is discussed.

With the increasing demand for automotive applications, the demand for power modules used in inverters for electric vehicles is also rising. To achieve the miniaturization of products, various power module topologies are being developed, and research on different power module topologies is actively progressing. In particular, power modules for single-phase or three-phase full-bridge inverters, which extend half-bridge circuits in parallel for motor drive applications, are being actively developed. However, the dynamic capacitance of a power module changes the loop impedance, leading to switching noise and making it essential for EMC issue analysis. In this paper, a simple two-port network theory-based method is proposed to extract the dynamic capacitance characteristics of multi-chip power modules. A method for extracting capacitance depending on dc bias in the switch-off state is introduced, and its validity is verified through simulations.

Common mode conducted EMI is a critical issue in power switching converters, particularly in automotive applications. Symmetrical topologies like two-switch flyback are effective in reducing EMI, but the delay between high-side and low-side switches can worsen the delivered EMI. This work investigates the use of the delay compensation technique in a GaN-based two-switch flyback converter. The study addresses both impedance balancing and delay effects on conducted EMI. Simulation results confirm a 25 dB reduction at 200 kHz with both delay compensation and impedance balancing compared to a traditional flyback converter.

Ensuring system-level power integrity (PI) is a critical challenge in high-performance computing (HPC) systems as power demands continue to rise. The voltage regulator module (VRM) plays a key role in stable power delivery, and its interaction with the power delivery network (PDN) must be carefully considered to prevent voltage fluctuations. This paper presents a system-level PI analysis incorporating a VRM behavior model for HPC system. The study examines (1) the impact of PDN impedance on VRM design, (2) the role of VRM bandwidth in minimizing PDN impedance, and (3) the influence of VRM bandwidth on decoupling capacitor effectiveness. The results demonstrate that accounting for PDN impedance in VRM design helps prevent instability and enables optimal performance tuning. Additionally, crossover frequency is a key factor in determining PDN impedance. Furthermore, when the frequency range dominated by the VRM overlaps with the effective range of decoupling capacitors, the impact of decaps is diminished. By considering this effect, increasing VRM bandwidth allows for an optimized design with fewer required decaps. These findings underscore the importance of VRM and PDN co-optimization in enhancing HPC system stability and efficiency.