Conference Agenda

Real-Time Operating Systems (RTOSes) play a crucial role in safety-critical domains, where deterministic and predictable task execution is essential. Yet they are increasingly exposed to ionizing radiation, which can compromise system dependability.

To assess FreeRTOS under such conditions, we introduce KRONOS, a software-based, non-intrusive post-propagation Fault Injection (FI) framework that injects transient and permanent faults into Operating System-visible kernel data structures without specialized hardware or debug interfaces. Using KRONOS, we conduct an extensive FI campaign on core FreeRTOS kernel components, including scheduler-related variables and Task Control Blocks (TCBs), characterizing the impact of kernel-level corruptions on functional correctness, timing behavior, and availability.

The results show that corruption of pointer and key scheduler-related variables frequently leads to crashes, whereas many TCB fields have only a limited impact on system availability.

While optimizing for core hardware performance-related target metrics, frameworks for approximate accelerators often overlook the reliability aspect. Approximated implementations obtained by these frameworks can potentially differ in terms of reliability and may impact the reliability of the overall system. In particular, approximation changes the data profiles transmitted between system modules, which can trigger crosstalk on interconnect lines and aggravate electromigration. We propose a two-stage process that performs a reliability assessment of the circuit interconnects after the approximate accelerator synthesis. Our approach aims to find the most reliable solutions from the approximate candidate circuits generated by an automated approximation flow. We then leverage Pareto-filtering to strike a balance between area, reliability, and accuracy. Notably, the selected designs achieve up to a 178% improvement in mission time compared to the original accelerator, and a 68\% improvement over designs optimized solely for area. In addition, our methodology allows custom priority settings to be adaptable to a user’s preference, thereby leading to circuits that meet diverse design constraints. Our experimental results show the effectiveness of our methodology in achieving superior trade-offs between area, reliability, and accuracy, hence uncovering a new dimension for approximate accelerator design methodologies.

Aging phenomena caused by various physical mechanisms may lead to a degradation of performance and reliability of an electronic system, hence limiting its expected lifetime. The paper presents an advanced, miniature design of an aging sensor with programmable delay logic and shows the results of integration of the sensor with a 5nm FinFET-based SRAM IP core. The sensor is implemented with a small number of logic gates, resulting in negligible overhead in area, power and delay. The sensor is equipped with power gating capability, which ensures that effect of aging is drastically reduced on sensor itself by selectively waking it up only during measurement cycles. Additionally, the paper is focused on control and bring up techniques of the aging sensors as well as the modeling approach of aging effect on the SRAM IP. Experimental results based on SPICE simulations demonstrate that proposed approach effectively detects memory response time degradation due to aging earlier than a functional error is observed at memory output. This solution enables mission-mode monitoring of memory operation, which is a critical aspect of silicon lifecycle management (SLM) framework.

The post-silicon integrated circuits (IC) testing is a very expensive process, especially in automotive industry where chip functionality has to be guaranteed by verifying multiple electrical parameters over a wide range of operating conditions. However, some costs can be avoided by reducing the amount of redundant tests, as certain parameters may exhibit a predictable behavior on the operating conditions variation. This paper presents a comparison between three approaches that use temperature parameters behavior for reducing the number of IC tests. The methods are tested on a production dataset consisting of 25 parameters and 300000 chips, results showing that the best method saves approximately 12% of the measurements.