Conference Agenda

Logic Locking aims to hide the original functionality

of the design using a secret key. It protects hardware intellectual

properties (IPs) against IP piracy or IC overproduction. However,

an attacker analyzes the structural traces and/or uses Boolean

satisfiability based technique called SAT attack to break such

logic locking schemes. This motivates us to find a SAT-hard logic

locking technique against structural analysis attacks. Therefore,

this paper introduces a novel multiplier-based logic locking

scheme. Leveraging the inherent complexity of multiplier circuits,

the proposed scheme exponentially increases the time required

for each iteration of a SAT attack. Moreover, a heuristic is also

proposed to identify appropriate locations for inserting multiplier

instances to increase the number of iterations. The multiplier-

based logic locking scheme is further combined with the Anti-

SAT scheme to create a robust and effective defense mechanism

against SAT attacks and the various other attacks exploiting

structural traces. The proposed technique is resilient to the state-

of-the-art attack dedicated to the existing compound logic locking

schemes. Moreover, the proposed compound logic locking scheme,

requires half the number of key inputs than the state-of-the-art

logic locking scheme while providing the similar level of security.

The standardization of post-quantum cryptography (PQC) has led to the adoption of ML-KEM, a lattice-based key encapsulation mechanism derived from CRYSTALS-Kyber. ML-KEM heavily relies on polynomial multiplication over the Module Learning With Errors (MLWE) problem, efficiently implemented using the Number Theoretic Transform (NTT). While the NTT significantly reduces computational complexity, its irregular memory access patterns and high arithmetic intensity pose challenges for efficient software execution, especially in constrained environments. Consequently, hardware acceleration has become essential for enabling practical ML-KEM deployment in embedded and edge systems.

Recent research has proposed several hardware accelerators for the NTT, but often without demonstrating their effectiveness in accelerating full matrix-vector products within ML-KEM. Designing such accelerators requires careful architectural trade-offs involving memory organization, data movement, parallelism, and system integration.

The main contribution of this paper is a comprehensive assessment of communication, memory arrangement, and architectural overheads in NTT accelerators. We analyze state-of-the-art NTT acceleration techniques for ML-KEM and we propose a hardware architecture optimized for efficient matrix-vector multiplication. Our NTT-based accelerator is integrated into a RISC-V System-on-Chip (SoC), and we evaluate the impact of key architectural choices (e.g., parallelism on the butterfly units, latency of communication and memory arrangement) on area and performance.

Mapping Binary Neural Networks (BNNs) on computation-in-memory (CIM) architectures enables a highly efficient approach for energy-constrained edge computing. In-memory processing significantly reduces critical performance bottlenecks in conventional architectures. Despite their efficiency, current optimized CIM implementations remain vulnerable to IP theft via side-channel analysis. This work investigates the side-channel leakage of a digital BNN-CIM accelerator that employs popcount-based accumulation. A range of circuit-level modifications in counter implementations are proposed and evaluated, exploring their impact on security metrics and design overhead. Results demonstrate that the Hamming weight (HW) and Hamming distance (HD) equalizing techniques combined with power equalization through duplication perform better than traditional dual-rail countermeasures. The findings provide practical guidance for designing secure and efficient peripheral components for popcount-based BNN accelerators.

Deep Neural Networks (DNNs) are widely deployed in safety-critical systems. In this regard, understanding the severity and mechanisms of security threats is essential for safeguarding the systems during deployment. This paper presents Multi-Target Bit Trojan (MTBT), the first bit-flip backdoor attack capable of simultaneously hijacking multiple target classes through minimal weight modifications. Unlike prior work that targets a single class, MTBT jointly optimizes trigger generation and weight perturbations to enable multi-target attacks with a single Trojan in CNN models. Our evaluation on an 8-bit quantized ResNet-18 demonstrates that MTBT achieves over 95% Attack Success Rate (ASR) for two target classes with only 55 bit flips, with a minimal impact on the baseline accuracy. Furthermore, MTBT successfully scales to three simultaneous targets, achieving a mean ASR exceeding 85% across all classes in CIFAR-10.