Conference Agenda

A SAT-hard Compound Logic Locking Scheme with Empirical Resistance to Known Structural Attacks

Sonali Shukla¹, Govind Jadhav¹, Durgesh Sardan¹, Suryakant Toraskar¹, Jaynarayn Tudu², Makoto Ikeda³, Masahiro Fujita³, Virendra Singh¹

1: Indian Institute of Technology Bombay, India; 2: Indian Institute of Technology Tirupati, India; 3: The University of Tokyo, Japan

Evaluating Communication and Architectural Overheads in NTT Accelerators for ML-KEM

Stefano Di Matteo^1,2, Emanuele Valea²

1: Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France; 2: Univ. Grenoble Alpes, CEA, List, F-38000 Grenoble, France

Periphery-Aware Power Side-Channel Hardening for Digital CIM-BNN Accelerators

Fouwad Jamil Mir^1,2, Abdullah Aljuffri¹, Said Hamdioui^1,2, Mottaqiallah Taouil^1,2

1: Delft University of Technology, The Netherlands; 2: CognitiveIC, Delft, The Netherlands

MTBT: Multi-Target Bit Trojan Attack for Quantized Neural Networks

Akiha Kusumoto, Mohammad Hasan Ahmadilivani, Jaan Raik

Tallinn University of Technology, Estonia

Experimental Analysis of FreeRTOS Dependability through Targeted Fault Injection Campaigns

Luca Mannella, Stefano Di Carlo, Alessandro Savino

Politecnico di Torino, Italy

Reliability Assessment in Approximate Accelerator Synthesis

Somayeh Sadeghi-Kohan¹, Muhammad Awais¹, Qazi Arbab Ahmed², Marco Platzner¹, Sybille Hellebrand¹, Thorsten Jungeblut², Hans-Joachim Wunderlich³

1: Paderborn University, Paderborn, Germany; 2: ReMi Research Group, University of Applied Sciences and Arts Bielefeld, Bielefeld, Germany; 3: University of Stuttgart, Stuttgart, Germany

On-Chip Sensor with Programmable Delay Logic to Monitor Memory Aging Evolution

Fabian Luis Vargas¹, Vache Galstyan², Gurgen Harutyunyan³, Yervant Zorian⁴

1: IHP – Leibniz Institute for High Performance Microelectronics, Germany; 2: Synopsys, USA; 3: Synopsys, USA; 4: Synopsys, USA

Ambient Parametric Test Reduction in Post-Silicon Production Testing via Temperature-Dependent Modelling: Three Approaches and a Case Study

Bianca Carbunescu-Stoenescu¹, Emilian David², Mihai Popovici³, Marina Topa¹, Valentina Davidoiu³, Andi Buzo⁴, Georg Pelz⁴

1: Technical University of Cluj Napoca, Romania; 2: Institute of Computer Science, Romanian Academy, Iasi Branch, Romania; 3: Infineon Technologies, Bucharest, Romania; 4: Infineon Technologies, AG Neubiberg, Germany

A Framework for Chiplet Authentication During Post-Stacking Test

Juan Suzano¹, Anthony Philippe³, Fady Abouzeid², Giorgio Di Natale¹, Philippe Roche²

1: TIMA; 2: ST Microelectronics; 3: CEA

A Model-Driven Approach to Variable-Frequency Clock Synthesis for PSN-Resilient IC Wake-Up

Vipin Kumar Singh¹, Vijay Pratap Yadav¹, Vassilis Alimisis^2,3, Paul P Sotiriadis^2,3, Shubhankar Majumdar⁴, Alak Majumder¹

1: NIT Arunachal Pradesh, India; 2: Archimedes, Athena Research Center, Marousi, Greece; 3: National Technical University of Athens, Greece; 4: NIT Meghalaya, India

Ageing Monitoring for Commercial Microcontrollers Based on Timing Windows

Leandro Lanzieri^1,2,3, Jiri Kral¹, Goerschwin Fey², Holger Schlarb¹, Thomas C. Schmidt³

1: Deutsches Elektronen-Synchrotron DESY, Germany; 2: Hamburg University of Technology, Germany; 3: Hamburg University of Applied Sciences, Germany

ANN-Based Ultra Fast Synthesis of Flash ADCs

Hakan Taşkıran, Abdullah Bayram, Engin Afacan

Gebze Technical University, Turkey (Türkiye)

Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing

Saeideh Nabipour¹, Chandan Kumar Jha², Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: Cyber-Physical Systems, DFKI GmbH, Germany; 2: University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

Comparative Analysis of Hardware Accelerator Architectures for Performance and Energy Efficient Deep Neural Network Execution

Salsabil Saoudi¹, Mario Barbareschi², Alberto Bosio¹

1: Ecole Centrale de Lyon, INSA Lyon, CNRS, Université Claude Bernard Lyon 1, CPE Lyon, INL (UMR 5270), 69130 Ecully, France; 2: University of Naples Federico II, Department of Electrical Engineering and Information Technologies, 80125 Naples, Italy

Efficient Co-Design of Networked Control Systems with 5G Configured Grant Scheduling

Yungang Pan¹, Max Nyberg Carlsson², Soheil Samii¹, Petru Eles¹, Zebo Peng¹

1: Embedded Systems Lab, Linköping University, Sweden; 2: Department of Automatic Control, Lund University, Sweden

Error Injecting Circuit: an Alternative to Discrete Gaussian Samplers

Andrea Marenco¹, Emanuele Valea¹, Elena Ioana Vatajelu²

1: CEA List; 2: TIMA-CNRS

Fan-In Aware Graph-Based Optimization for MAC-Based In-Memory Computing

Fatemeh Shirinzadeh¹, Abhoy Kole¹, Kamalika Datta^1,2, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: German Research Centre for Artificial Intelligence (DFKI), Germany; 2: Institute of Computer Science, University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Germany

Monolithic quantum random number generator containing Si-LED, SPAD and analog processing

Horst Zimmermann, David Bugl, Bernhard Goll, Michael Hofbauer, Kerstin Schneider-Hornstein, Hiwa Mahmoudi

TU Wien, Austria

Pulsed Electromagnetic Fault Injection on RO-based True Random Number Generators in FPGAs

Sami El Amraoui¹, Mahdi Allaw¹, Florian Pebay-Peyroula², Régis Leveugle¹, Paolo Maistri¹

1: Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA; 2: CEA-Leti

Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures

Spandan Das¹, Sayak Deb², Khushboo Qayyum³, Sallar Ahmadi-Pour¹, Christoph Lüth^1,3, Rolf Drechsler^1,3

1: Institute of Computer Science, University of Bremen, Bremen, Germany; 2: Institute of Physics and Electrical Engineering, University of Bremen, Bremen, Germany; 3: Cyber-Physical Systems, DFKI GmbH, Bremen, Germany

BLAR-3D: Beta-Regulated Learning-Based Adaptive Routing for 3D Network-on-Chip

Cevdet Aslan, Suleyman Tosun

Hacettepe University, Turkey (Türkiye)

Influence of Temperature Variations on the Frequency of Two-dimensional MEMS Mirrors

Marlene Alexandra Schneider^1,2, Norbert Druml², David Brunner²

1: Technische Universität Graz; 2: Infineon Technologies Austria AG

A Wideband Q/V Band Cascode Darlington Power Amplifier using Transmission Line Transformer and Current-reuse Techniques

Chin-Wei Kuo¹, Hsin-Chieh Lin², Chien-Nan Kuo³, Hwann-Kaeo Chiou¹

1: National Central University, Taoyuan,Taiwan; 2: Taiwan Semiconductor Research Institute, National Institutes of Applied Research, Hsinchu, Taiwan; 3: National Yang Ming Chiao Tung University, Hsinchu, Taiwan

A 320.3 fJ/bit UCIe Advanced Package TX Driver in 28 nm FDSOI

Patryk Kozicki¹, Viki Szortyka¹, Witold Pleskacz²

1: Cadence Design Systems, Poland; 2: Warsaw University of Technology, Institute of Microelectronics & Optoelectronics

Integrated Gate Driver with Adaptive Dead-Time Control and Gate-Drive Boost for High-Efficiency BCD Synchronous Buck Converters

Fahd Khan¹, Niccolo' Brambilla², Sandro Rossi², Calogero Ribellino³, Edoardo Bonizzoni¹, Piero Malcovati¹

1: Department of Electrical, Computer and Biomedical Engineering, University of Pavia, Italy; 2: STMicroelectronics, Smart Power TR&D, Castelletto, Italy; 3: STMicroelectronics, R&D, Catania, Italy

Silicon-Proven Low-Dropout Regulator Designed in 65nm CMOS Technology

David Maljar, Róbert Ondica, Daniel Arbet, Martin Kováč, Viera Stopjaková

Slovak University of Technology, Faculty of Electrical Engineering and Information Technology, Slovak Republic

Embedded Tutorial: AI vs. Verification Engineer: Fight or Synergy?

Marcela Zachariášová

Brno University of Technology, Czech Republic (Czechia)

Assessing the Vulnerability of Open-Source RISC-V Processors to Transient Execution Attacks

Elia Lazzeri¹, Gianluca Furano², Luca Cassano¹

1: Politecnico di Milano, Italy; 2: European Space Agency, The Netherlands

Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates

Abhoy Kole¹, Till Schnittka², Rolf Drechsler^1,2

1: DFKI, Germany; 2: University of Bremen, Germany

Co-Optimizing Performance and Security of Analog Integrated Circuits

Abdullah Bayram¹, Haralampos-G. Stratigopoulos², Engin Afacan¹

1: Gebze Technical University, Turkey (Türkiye); 2: Sorbonne Université, CNRS, LIP6 (France)

A Power-Efficient Analog Hardware Swish-Based Artificial Neural Network Architecture for Star Evolutionary Phase Classification

Andreas Papathanasiou¹, Vassilis Alimisis², Alak Majumder³, Paul P. Sotiriadis¹

1: National Technical University of Athens; 2: Archimedes, Athena Research Center, Greece; 3: National Institute of Technology, Arunachal Pradesh, Pin-791113, India

A CMOS 72kHz–123MHz Tunable Oscillator for Low-Power IoT Applications

Robert Ondica, Daniel Arbet, Martin Kováč, Miroslav Potočný, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic

CAD Software for the Detection of Floating Metals for Advanced CMOS Technologies

Sweekriti Patle¹, Marika Grochowska¹, Witold Pleskacz²

1: Cadence Design System, Poland; 2: Warsaw University of Technology, Poland

Optimizing Edge AI: Current Challenges and the Neuromorphic Outlook

Milan Dinčić¹, Davide Bertozzi², Alice Bizzarri³, Rizwan Tariq Syed⁴, Edward Jones²

1: University of Niš, Faculty of Electronic Engineering, Serbia; 2: University of Manchester, United Kingdom; 3: University of Ferrara, Italy; 4: IHP – Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany

DP-MCTS: Deep Playout-Driven MCTS for Approximate Accelerator Design

Muhammad Awais¹, Hassan Ghasemzadeh Mohammadi², Sayed Morteza Jawadi¹, Marco Platzner¹

1: Paderborn University, Paderborn Germany; 2: Reneo Group GmbH, Hamburg, Germany

FRAPPE: Feasibility Report on Accelerating Payload Pattern-matching Engines in Intrusion Detection Systems with FPGAs

Lukas Sismis¹, Jan Korenek²

1: CESNET z. s. p. o., Czech Republic (Czechia); 2: Faculty of Information Technology, Brno University of Technology

A Parallel FPGA Architecture for Data Clustering using the Potts Model

Xingjian Gao, Jie Han

University of Alberta, Canada

Investigation of MPPT Control for Hybrid Voltage Converter in Low-Power Energy Harvesters

Martin Kováč, Róbert Ondica, Richard Bagín, Daniel Arbet, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic

Conditional Variational Autoencoders for Statistical MOSFET Modeling

Dawid Sudowski¹, Dominik Kasprowicz²

1: Rail-Mil Sp. z o.o., 03-994 Warsaw, Poland; 2: Warsaw University of Technology, 00-665 Warsaw, Poland

Harmonic-Controlled Bandpass Filter With Upper Stopband Suppression for 6G Applications

Sanghoon Jeong, Juseop Lee

College of Informatics, Korea University, Seoul, South Korea

Embedded Tutorial Considerations on the Design of Resilient System-in-Package Based on On-Chip Lifecycle Management

Fabian Luis Vargas

IHP – Leibniz Institute for High Performance Microelectronics, Germany