Conference Agenda

Keynote 3
Thursday, 25/Apr/2019:
1:30pm - 2:30pm

Session Chair: Zoran Stamenkovic, IHP
Location: Doubletree by Hilton City Plaza


Can New Defect Models Help Eliminate System Level Tests?

Adit D. Singh

Dept. of Electrical & Computer Engineering - Auburn University, US

ICs have long been tested for manufacturing defects using low cost scan tests. However, such structural tests no longer appear sufficient in ensuring the required test quality for complex processor SOCs. Expensive System Level Tests (SLTs), that temporarily mount the SOC on a test board closely replicating the target hardware application, are increasing being used to perform extensive functional testing as a final defect screen. In this talk we discuss the effectiveness of the advanced new defect models such as cell aware, timing aware cell aware, gate exhaustive, TSOF, etc. that have been introduced to improve the defect coverage of scan tests and thus minimize the need for SLTs. We also consider failure mechanisms that may be missed by even these new tests, in particular, timing failures resulting from an accumulation of the delays caused by random process variations.