Poster Session 2
A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider
Department of Electrical Engineering, National Central University, Taiwan
This paper presents a 5-10.5 GHz wideband fully-integrated I/Q transmitter in tsmcTM 90-nm CMOS technology. A current-mode passive mixer was adopted to enhance the linearity and low-power performance. The transmitter also integrated current-mode logic (CML) frequency divider (FD) to generate I/Q signals at LO-port. The I/Q signals were directly combined by using high-Q top-metal lines. An inductively coupled resonator (ICR) wideband output matching network was used to transform balance to unbalance output signal in RF drive-amplifier. The proposed transmitter achieves a 3-dB bandwidth from 5 to 10.5 GHz, a conversion gain of 12.9 dB, an output P1dB of -4.17 dBm, an output IP3 of 16.47 dBm, a carrier suppression of 30.02 dBc and a sideband suppression of 39.62 dBc under an LO power of 14 dBm at the center frequency of 8 GHz. The chip consumed dc power of 66.36 mW. The chip dimensions, including all RF and DC pads, are 1.25 ×1.1 mm2.
FPGA-based SIFT Implementation for Wearable Computing
1Technology and Bionics, Pázmány Péter Catholic University Faculty of Information, Hungary; 2Laboratoire Bordelais de Recherche en Informatique, University of Bordeaux, France; 3Institut de Neurosciences Cognitives et Intégratives d'Aquitaine, University of Bordeaux, France
The article describes the first steps to achieve control over a robotic or prosthetic arm based on analysis of visual environment acquired in real-time by video cameras on glasses and on the prosthesis. One of the main goals of the research is to develop a wearable, portable, lightweight, and low power consumption device for visual scene analysis. This paper will discuss the critical steps of its implementation on an FPGA board.
We implemented some time-consuming parts of the SIFT algorithm needed for the analysis in C/C++ language on TUL PYNQ-Z2 FPGA board.
This implementation allows for a low power consumption of the programmable logic part of the system. The obtained value is 0.274W. Processing capacity is 96.45 images per second on a small wearable size device which allow for the real-time implementation of the whole analysis in the future.
Using Voters May Lead to Secret Leakage
Czech technical University in Prague, Czech Republic
The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.
Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology
Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, Slovak Republic
This paper deals with cross-implementation of analytical and physical fundamentals of ultra low-voltage charge pumps. The analysis is based on precise, general formulas including characteristic parasitic effects valid for linear charge pumps. The parasitic effects are extended by nonlinear parasitic capacitances represented as equivalent linear model of a switched transistor itself. The discussion about nonlinear and linear behaviour of these parasitics is also included and demonstrated using cross-coupled, dynamic threshold implementation, where the EKV model of transistors has been utilized. The paper also introduced a new design rule for design of charge pumps based on transistors working in sub-threshold region to maximize the power throughput. This is achieved by tuning the operation conditions to the boundary case.
New Categories of Safe Faults in a Processor-Based Embedded System
1Politecnico di Torino, Dip. Automatica e Informatica - Torino, Italy; 2Tallinn University of Technology - Tallinn, Estonia
The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some new classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults associated belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed approach requires an analysis of the processor at the RT level and the use of an ATPG tool with specific constraints on Primary Inputs (PIs) or Primary Output (POs) of some units inside the processor. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.