Conference Agenda

Session 6: HW Design at Application-Level
Friday, 26/Apr/2019:
2:00pm - 3:30pm

Session Chair: Petr Fišer, Czech Technical University in Prague
Location: Doubletree by Hilton City Plaza


Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines

Vlad Muresan, Mihail Abrudean

UTCN, Romania

In this paper, a solution to control the servicing machines of a rotary hearth furnace is presented. The proposed control strategy is based on the usage of a modified cascade control structure. The proposed control solution is augmented with a fault detection system capable to detect the faults which frequently occur in the operation of the D.C. motors used to drive the servicing machines. It is proved through simulation that, in a certain range of faults magnitude, their effect is rejected by the controllers, aspect which makes the proposed control system a fault tolerant one. Also, due to the usage of neural reference model, the faults magnitude can be quantified and when the safety limits are reached, some decisions for reducing the servicing machines operation are automatically generated.

Hardware and Control Design of a Ball Balancing Robot

Ioana Lal1, Marius Nicoara1, Alexandru Codrean2, Lucian Busoniu2

1Robert Bosch, Romania; 2Technical University of Cluj-Napoca, Romania

This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and agility lead to the choice of ball, motors, gears, omnidirectional wheels, and body frame. The electronic hardware architecture is presented in detail, together with timing results showing that real-time control can be achieved. Finally, we design a linear quadratic regulator for balancing, starting from a 2D model of the robot. Experimental balancing results are satisfactory, maintaining the robot in a disc 0.3 m in diameter.

A hardware friendly rational function approximation evaluator

Silviu-Ioan Filip

Inria, France

In this talk I will present an automatic method for the high throughput evaluation of functions via polynomial or rational approximations and its hardware implementation, on FPGAs. These approximations are evaluated using Ercegovac’s iterative E-method adapted for FPGA implementation. We discuss how the polynomial and rational function coefficients are optimised so that they satisfy the constraint of the E-method. We present several examples of practical interest; in each case a resource-efficient approximation is proposed and comparisons are made with alternative approaches.