Session 1: Security & Safety
Encryption-Based Secure JTAG
1LIRMM - CNRS, Montpellier, France; 2TIMA - CNRS, Grenoble, France
Standard test infrastructures, such as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG), are widely used in nowadays Integrated Circuits (ICs). However, they pose an important security challenge to the designers because of the high controllability and observability they offer through the Test Access Port (TAP). For instance, malicious users can exploit test infrastructures in order to access the internal scan chains of crypto-cores and perform scan attacks. Moreover, these infrastructures connect all the devices of the system to the same network. For this reason, the data sent to a target device are potentially visible to all the others. Consequently, this poses a threat to the confidentiality of data content. The encryption of test data is a countermeasure that has been conceived in order to overcome these threats. In this paper, we propose a new secure version of the JTAG infrastructure, relying on stream-based encryption.
Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing
1University of New South Wales; 2University of Peradeniya
We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4,5% area and 9,1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.
Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems
Slovak University of Technology in Bratislava, Slovak Republic
This paper presents a novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations. Due to very low and constant latency of these operations with respect to the actual number and location of free blocks of memory, the proposed solution is suitable for hard real-time and mixed-criticality systems. The proposed hardware-accelerated memory manager implements Worst-Fit algorithm for selection of a suitable free block of memory that can be used by the external environment, e.g. CPU or any custom hardware. The proposed solution uses hardware-accelerated max queue, which is a data structure that continuously provides the largest free memory block in two clock cycles regardless of the actual number or constellation of available free blocks. The proposed memory manager was verified using simplified version of UVM and applying billions of randomly generated instructions as test inputs. A synthesis into Intel FPGA Cyclone V was performed, and the synthesis results are presented as well. The memory manager was also synthesized into 28 nm technology with 1 GHz clock frequency and the power supply voltage of 0.9 V. The ASIC synthesis results show that the proposed memory manager consumes additional chip area from 35% to 70% of the managed memory.