Conference Agenda

Session 3: Analog Circuit Design & Test
Thursday, 25/Apr/2019:
10:30am - 12:00pm

Session Chair: Witold Pleskacz, Warsaw University of Technology
Location: Doubletree by Hilton City Plaza


High Side Power MOSFET Switch Driver for a Low-power AC/DC Converter

Miroslav Potočný, Juraj Brenkuš, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic

With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions need to be provided. In this paper, we propose a solution that is optimized for operation with output loads up to 500 mW, while high efficiency and close to zero no-load consumption have been our foremost design goals. The proposed design is implemented in a high-voltage CMOS process and transistor level simulation results show improved properties of the proposed solution over the existing ones.

Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Viera Stopjakova

Slovak University of Technology, Slovak Republic

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in standard twin-well 130 nm CMOS technology. The nominal power supply voltage was set to V DD = 0.4 V and the working temperature range was set to industrial standard -20 ◦ C – 85 ◦ C. The proposed comparator design is intended to work in energy harvesting system. Hence, low power consumption is a key requirement. It employs bulk-driven transistors at the input stage and operates in so-called current mode. The addressed comparator circuit draws less then 5 μA in typical conditions but its function and robustness has been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

A New FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network

Sergei Odintsov1, Ludovica Bozzoli2, Corrado De Sio2, Luca Sterpone2, Artur Jutman1

1Tallinn University of Technology; 2Politecnico di Torino

Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA) with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various sub-systems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.