Conference Agenda

Poster Session 1
Wednesday, 24/Apr/2019:
3:30pm - 4:00pm

Location: Doubletree by Hilton City Plaza


Generic Error Localization Methodology for the Design at the Electronic System Level

Sebastian Pointner1, Pablo González de Aledo2, Robert Wille1

1Johannes Kepler University Linz, Austria; 2Imperial College London, UK

The ever increasing complexity of embedded systems poses significant challenges to designers and motivates to verify a system and consequently debug errors already in early phases of the design process, e.g. at the Electronic System Level (ESL). To this end, several methods and tools such as assertion checkers, property checkers, symbolic executers, and more have been proposed. However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose the idea of a generic error localization methodology, which aids the designer in error localization without the need to change the respectively utilized verification method. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today (including possible updates and newly proposed ones in the future). The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.

A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System

Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng

National Central University, Taiwan

Since 2011, due to the growth in the amount of information, the innovation of learning algorithms and the improvement of computer technology make the application of artificial intelligence feasible in a wide range of fields. This paper presents a sketch classifier technique with deep learning models. We use the depth-wise convolution layer to lighten the deep neural network. The result shows the improvement in approximately 1/5 of computation. We use Google Quick Draw dataset to train and evaluate the network, which can have 98% accuracy in 10 categories and 85% accuracy in 100 categories. Finally, we realize it on STM32F469I Discovery development board for demonstration. The system can achieve real-time implementation of sketch classification.

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers

Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh

National Cheng Kung University, Taiwan

Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. Resolving conflicts is non-trivial due to the fact that the memory access pattern of the detection task depends on the trained result. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.

Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems

Ching-Hwa Cheng

Feng Chia University, Taiwan

A built-in digitalized power management (DPMM) and voltage domain programmable (VDP) mechanisms are proposed to design a low-power system. In the proposed techniques, the high and low voltages applied to logic modules can be switchable. This flexible voltage-domain assignment allows the chip performance and power consumption can dynamically adjust during circuit operation. To support the DPMM and VDP mechanisms, the voltage-level monitor circuit and power-switch circuit are designed to support multiple operation modes for DPMM-VDP digital circuit designs. A powerless retention flip-flop is developed for temporary data storage during voltage domain dynamically switching. While to prevent the system failure come from voltage integrity problem, a built-in voltage-level monitoring mechanism is utilized to monitor voltage integrity during VDP circuit operation. The proposed mechanism allows the chip performance and power consumption to be flexibly adjusted during circuit operation. Two physical implementation chips and measured results proof of this methodology has 30~55% power reduction comparisons with using single-Vdd.

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

Martin Stava

Brno University of Technology, Czech Republic

This paper presents a novel online fault tolerance method for network-on-chip interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. The other concept of monitoring errors separately on two types of interconnects [3] – inter-switch links and intra-switch input/output port paths – is also employed. Both the concepts allow more efficient routing when compared to existing error recovery schemes. Experimental validation shows that the proposed scheme delivers better or at least similar performance when compared to existing NoC error recovery schemes.

Fault-Aware Performance Assessment Approach for Embedded Networks

Jan Malburg1, Karl Janson2, Jaan Raik2, Frank Dannenmann1

1German Aerospace Center, Bremen, Germany; 2TalTech, Tallinn, Estonia

Current embedded systems are more and more using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4x4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.

Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung-Han Tsai1, Yuan-Chen Ho1, Ming-Hwa Sheu2

1National Central University, Taiwan; 2National Yunlin University of Science and Technology

At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages on low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.