Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
Session Overview
Date: Wednesday, 24/Apr/2019
9:00am
-
9:30am
Opening
Location: Casino Urban Culture Center
9:30am
-
10:30am
Keynote 1
Location: Casino Urban Culture Center
Chair: Liviu-Cristian Miclea, Technical University of Cluj-Napoca
 

The Power of Computation-in-Memory: Beyond von Neumann and Beyond CMOS

Said Hamdioui

Delft University of Technology, the Netherlands

10:30am
-
11:00am
Coffee Break + IoT Contest
Location: Casino Urban Culture Center
11:00am
-
12:00pm
Keynote 2
Location: Casino Urban Culture Center
Chair: Alberto Bosio, ECL INL
 

Towards embedding attack detection on Systems-on-Chip

Anca Molnos

CEA, France

12:00pm
-
2:00pm
Lunch
Location: Doubletree by Hilton City Plaza
2:00pm
-
3:30pm
Session 1: Security & Safety
Location: Doubletree by Hilton City Plaza
Chair: Gyorgy Cserey, Pazmany Peter Catholic University
 

Encryption-Based Secure JTAG

Emanuele Valea1, Mathieu Da Silva1, Marie-Lise Flottes1, Giorgio Di Natale2, Bruno Rouzeyre1

1: LIRMM - CNRS, Montpellier, France; 2: TIMA - CNRS, Grenoble, France


Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing

Amin Malekpour1, Roshan Ragel2, Daniel Murphy1, Aleksandar Ignjatovic1, Sri Parameswaran1

1: University of New South Wales; 2: University of Peradeniya


Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems

Lukas Kohutka, Lukas Nagy, Viera Stopjakova

Slovak University of Technology in Bratislava, Slovak Republic

3:30pm
-
4:00pm
Poster Session 1
Location: Doubletree by Hilton City Plaza
 

Generic Error Localization Methodology for the Design at the Electronic System Level

Sebastian Pointner1, Pablo González de Aledo2, Robert Wille1

1: Johannes Kepler University Linz, Austria; 2: Imperial College London, UK


A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System

Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng

National Central University, Taiwan


Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers

Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh

National Cheng Kung University, Taiwan


Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems

Ching-Hwa Cheng

Feng Chia University, Taiwan


Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

Martin Stava

Brno University of Technology, Czech Republic


Fault-Aware Performance Assessment Approach for Embedded Networks

Jan Malburg1, Karl Janson2, Jaan Raik2, Frank Dannenmann1

1: German Aerospace Center, Bremen, Germany; 2: TalTech, Tallinn, Estonia


Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung-Han Tsai1, Yuan-Chen Ho1, Ming-Hwa Sheu2

1: National Central University, Taiwan; 2: National Yunlin University of Science and Technology

4:00pm
-
4:30pm
Industrial Session: Trends and Challenges in Automotive Semiconductor Development
Location: Doubletree by Hilton City Plaza
Chair: Paolo Bernardi, Politecnico Di Torino
 

Trends and Challenges in Automotive Semiconductor Development

Charlotte Rohr

Bosch

4:30pm
-
6:00pm
Special Session: From Constraints to Tape-Out: Towards a Continuous AMS Design Flow
Location: Doubletree by Hilton City Plaza
Chair: Manfred Dietrich, Dikuli Unternehmensberatung
 

Flexible Generation of Analog Integrated Layouts Using a Novel Floorplanning-Driven P&R Approach

Benjamin Prautsch1, Uwe Hatnik1, Jens Lienig2, Jens Benndorf3

1: Fraunhofer IIS/EAS Dresden; 2: TU Dresden; 3: Dream Chip Technologies GmbH


Invasive Analysis Framework for non-functional Effect Verification

Georg Gläser1, Martin Grabmann1, Dirk Nuernbergk2

1: IMMS GmbH; 2: Melexis GmbH


Resolving Dependencies in Hierarchical AMS Designs Using Constraint Propagation and Budgeting

Andreas Krinke1, Tilman Horst1, Jens Lienig1, Goeran Jerke2

1: TU Dresden; 2: Robert Bosch GmbH


Schematic Generation Framework in a Mixed Signal Top Down Design Flow

Tobias Markus1, Markus Mueller2, Ulrich Brue-ning3

1: ZITI University Heidelberg; 2: Extoll GmbH; 3: Universität Heidelberg

6:30pm
-
8:00pm
Welcome dinner
Location: Doubletree by Hilton City Plaza
Date: Thursday, 25/Apr/2019
8:30am
-
10:00am
Session 2: On-line Test & Reliability
Location: Doubletree by Hilton City Plaza
Chair: Alberto Bosio, ECL INL
 

Hybrid On-line Self-test Architecture for Computational Units on Embedded Processor Cores

Andrea Floridia, Ernesto Sanchez, Davide Piumatti, Gianmarco Mongano

Politecnico di Torino, Italy


On the In-field Test of GPGPU Scheduler Memory

Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Stefano Di carlo

Politecnico di Torino, Italy


Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Marco Restifo1, Matteo Sonza Reorda1, Paolo Bernardi1, Felipe Almeida1, Deborah Calabrese1, Davide Appello2, Roberto Ugioli2, Vincenzo Tancorre2, Giulio Zoppi2

1: Politecnico di Torino, Italy; 2: STMicoelectronics, Italy

10:00am
-
10:30am
Poster Session 2
Location: Doubletree by Hilton City Plaza
 

A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider

Hwann-Kaeo Chiou, Wei-Min Sung

Department of Electrical Engineering, National Central University, Taiwan


FPGA-based SIFT Implementation for Wearable Computing

Attila Fejér1,2, Zoltán Nagy1, Jenny Benois-Pineau2, Péter Szolgay1, Aymar de Rugy3, Jean-Philippe Domenger2

1: Technology and Bionics, Pázmány Péter Catholic University Faculty of Information, Hungary; 2: Laboratoire Bordelais de Recherche en Informatique, University of Bordeaux, France; 3: Institut de Neurosciences Cognitives et Intégratives d'Aquitaine, University of Bordeaux, France


Using Voters May Lead to Secret Leakage

Jan Belohoubek, Petr Fiser, Jan Schmidt

Czech technical University in Prague, Czech Republic


Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology

Martin Kovac, Daniel Arbet, Viera Stopjakova, Michal Sovcik

Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, Slovak Republic


New Categories of Safe Faults in a Processor-Based Embedded System

Davide Piumatti1, Matteo Sonza Reorda1, Cemil Cem Gursoy2, Maksim Jenihhin2, Stephen Oyeniran2, Jaan Raik2, Raimund Ubar2

1: Politecnico di Torino, Dip. Automatica e Informatica - Torino, Italy; 2: Tallinn University of Technology - Tallinn, Estonia

10:30am
-
12:00pm
Session 3: Analog Circuit Design & Test
Location: Doubletree by Hilton City Plaza
Chair: Witold Pleskacz, Warsaw University of Technology
 

High Side Power MOSFET Switch Driver for a Low-power AC/DC Converter

Miroslav Potočný, Juraj Brenkuš, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic


Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Viera Stopjakova

Slovak University of Technology, Slovak Republic


A New FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network

Sergei Odintsov1, Ludovica Bozzoli2, Corrado De Sio2, Luca Sterpone2, Artur Jutman1

1: Tallinn University of Technology; 2: Politecnico di Torino

12:00pm
-
1:30pm
Lunch
Location: Doubletree by Hilton City Plaza
1:30pm
-
2:30pm
Keynote 3
Location: Doubletree by Hilton City Plaza
Chair: Zoran Stamenkovic, IHP
 

Can New Defect Models Help Eliminate System Level Tests?

Adit D. Singh

Dept. of Electrical & Computer Engineering - Auburn University, US

3:00pm
-
11:00pm
Social Event
Date: Friday, 26/Apr/2019
9:00am
-
10:30am
Session 4: HW Design for Communication Networks
Location: Doubletree by Hilton City Plaza
Chair: Dominik Macko, Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava
 

Modular Data Link Layer Processing for THz Communication

Lukasz Lopacinski1, Mohamed Hussein Eissa1, Goran Panic1, Alireza Hasani1,2, Rolf Kraemer1,2

1: IHP – Leibniz-Institut für innovative Mikroelektronik, Germany; 2: Brandenburgische Technische Universität Cottbus - Senftenberg


Hash-based Pattern Matching for High Speed Networks

Tomáš Fukač, Jan Kořenek

Faculty of Information Technology Brno University of Technology, Czech Republic


Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic

Roman Vrána, Jan Kořenek, David Novák

Faculty of Information Technology, Brno University of Technology, Czech Republic

10:30am
-
11:00am
Poster Session 3
Location: Doubletree by Hilton City Plaza
 

Nonlinear Compression Codes Used In IC Testing

Ondrej Novak

TU Liberec, Czech Republic


Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI’s Components using RAD-THERM TCAD Subsystem

Konstantin Petrosyants1, Maxim Kozhukhov2, Dmitry Popov1

1: National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia; 2: JC ‘VNIIEM Corporation’, Moscow, Russia


Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430

Karel Szurman, Zdenek Kotasek

Faculty of Information Technology, Brno University of Technology, Czech Republic


Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime

Kai-Hsun Chen2, Ching-Yuan Chen1, Jiun-Lang Huang1,2

1: Graduate Institute of Electronics Engineering (GIEE), National Taiwan University, Taipei, Taiwan; 2: Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan


Comparison of Nearest Neighbours Algorithms for PET Image Reconstruction on FPGA

Zoltan Nagy1, Andras Kiss1, Levente Mark Santha1,2, Kristof Karacs1

1: Pázmány Péter Catholic University, Budapest, Hungary; 2: Institute for Computer Science and Control Hungarian Academy of Sciences, Budapest, Hungary


A Global Sensitivity Analysis Method Based on Local Regression

Ingrid Kovacs1, Alexandra Iosub2, Marina Topa1, Andi Buzo3, Georg Pelz3

1: Technical University of Cluj-Napoca, Romania; 2: Gheorghe Asachi Technical University of Iași, Romania; 3: Infineon Technologies AG, Neubiberg, Germany

11:00am
-
12:30pm
Session 5: Student Session
Location: Doubletree by Hilton City Plaza
Chair: Ondrej Novak, TU Liberec
 

Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter

Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold Adam Pleskacz

Warsaw University of Technology, Poland


Analyzing and Optimizing the Dummy Rounds Scheme

Stanislav Jeřábek, Jan Schmidt

Czech Technical University in Prague, Czech Republic


Automated Integration of Dynamic Power Management into FPGA-Based Design

Michal Škuta, Dominik Macko

Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava, Slovak Republic


Development of Wearable Hardware Platform to Measure the ECG and EMG with IMU to Detect Motion Artifacts

Muhammad TANWEER, Kari Halonen

Aalto University, Finland

12:30pm
-
2:00pm
Lunch
Location: Doubletree by Hilton City Plaza
2:00pm
-
3:30pm
Session 6: HW Design at Application-Level
Location: Doubletree by Hilton City Plaza
Chair: Petr Fišer, Czech Technical University in Prague
 

Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines

Vlad Muresan, Mihail Abrudean

UTCN, Romania


Hardware and Control Design of a Ball Balancing Robot

Ioana Lal1, Marius Nicoara1, Alexandru Codrean2, Lucian Busoniu2

1: Robert Bosch, Romania; 2: Technical University of Cluj-Napoca, Romania


A hardware friendly rational function approximation evaluator

Silviu-Ioan Filip

Inria, France

3:30pm
-
4:00pm
Closing Session
Location: Doubletree by Hilton City Plaza

 
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