Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

Session Overview
Date: Wednesday, 24/Apr/2019
9:00am - 9:30amOpening
Casino Urban Culture Center 
9:30am - 10:30amKeynote 1
Session Chair: Liviu-Cristian Miclea, Technical University of Cluj-Napoca
Casino Urban Culture Center 

The Power of Computation-in-Memory: Beyond von Neumann and Beyond CMOS

Said Hamdioui

Delft University of Technology, the Netherlands

Today’s and emerging applications are extremely demanding in terms of storage and computing power. Data-intensive/big-data applications and internet-of-things (IoT) will transform the future; they will not only impact the all aspects of our life, but also change a lot in the IC and computer world. Emerging applications require computing power which was typical of supercomputers a few years ago, but with constraints on size, power consumption and guaranteed response time which are typical of the embedded applications. Both today’s computer architectures and device technologies (used to manufacture them) are facing major challenges making them incapable to deliver the required functionalities and features. In order for computing systems to continue deliver sustainable benefits for the foreseeable future society, alternative computing architectures and notions have to be explored in the light of emerging new device technologies.

10:30am - 11:00amCoffee Break + IoT Contest
Casino Urban Culture Center 
11:00am - 12:00pmKeynote 2
Session Chair: Alberto Bosio, ECL INL
Casino Urban Culture Center 

Towards embedding attack detection on Systems-on-Chip

Anca Molnos

CEA, France

Connected devices are increasingly targeted by cyber-security attacks. Such attacks may exploit software bugs, e.g., to install malware, and can go as far as physically interfering with the device by, e.g., side channel attacks or fault attacks to recover secret keys. Software and physical attacks can be combined, and give place to mixed, powerful means to gain control of a system.

Attack detection is a field that receives more and more attention because it has the potential to address several attacks at once. Machine learning methods can be applied in two steps. An off-line characterisation of the logical and physical properties of the Systems-on-Chip can give an idea about what is the nominal behaviour of the system. Run-time monitoring may determine if there are deviations from this behaviour. This talk will survey recent approaches for attack detection on Systems-on-Chip, for malware, memory attacks, and side-channel attacks. Furthermore our results on the utilisation of binary classification to design lightweight memory access detectors will be presented. Finally we will discuss the need to monitor heterogeneous features, e.g., physical, architectural and software, and future directions for research.

12:00pm - 2:00pmLunch
Doubletree by Hilton City Plaza 
2:00pm - 3:30pmSession 1: Security & Safety
Session Chair: Gyorgy Cserey, Pazmany Peter Catholic University
Doubletree by Hilton City Plaza 

Encryption-Based Secure JTAG

Emanuele Valea1, Mathieu Da Silva1, Marie-Lise Flottes1, Giorgio Di Natale2, Bruno Rouzeyre1

1LIRMM - CNRS, Montpellier, France; 2TIMA - CNRS, Grenoble, France

Standard test infrastructures, such as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG), are widely used in nowadays Integrated Circuits (ICs). However, they pose an important security challenge to the designers because of the high controllability and observability they offer through the Test Access Port (TAP). For instance, malicious users can exploit test infrastructures in order to access the internal scan chains of crypto-cores and perform scan attacks. Moreover, these infrastructures connect all the devices of the system to the same network. For this reason, the data sent to a target device are potentially visible to all the others. Consequently, this poses a threat to the confidentiality of data content. The encryption of test data is a countermeasure that has been conceived in order to overcome these threats. In this paper, we propose a new secure version of the JTAG infrastructure, relying on stream-based encryption.

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing

Amin Malekpour1, Roshan Ragel2, Daniel Murphy1, Aleksandar Ignjatovic1, Sri Parameswaran1

1University of New South Wales; 2University of Peradeniya

We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4,5% area and 9,1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.

Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems

Lukas Kohutka, Lukas Nagy, Viera Stopjakova

Slovak University of Technology in Bratislava, Slovak Republic

This paper presents a novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations. Due to very low and constant latency of these operations with respect to the actual number and location of free blocks of memory, the proposed solution is suitable for hard real-time and mixed-criticality systems. The proposed hardware-accelerated memory manager implements Worst-Fit algorithm for selection of a suitable free block of memory that can be used by the external environment, e.g. CPU or any custom hardware. The proposed solution uses hardware-accelerated max queue, which is a data structure that continuously provides the largest free memory block in two clock cycles regardless of the actual number or constellation of available free blocks. The proposed memory manager was verified using simplified version of UVM and applying billions of randomly generated instructions as test inputs. A synthesis into Intel FPGA Cyclone V was performed, and the synthesis results are presented as well. The memory manager was also synthesized into 28 nm technology with 1 GHz clock frequency and the power supply voltage of 0.9 V. The ASIC synthesis results show that the proposed memory manager consumes additional chip area from 35% to 70% of the managed memory.

3:30pm - 4:00pmPoster Session 1
Doubletree by Hilton City Plaza 

Generic Error Localization Methodology for the Design at the Electronic System Level

Sebastian Pointner1, Pablo González de Aledo2, Robert Wille1

1Johannes Kepler University Linz, Austria; 2Imperial College London, UK

The ever increasing complexity of embedded systems poses significant challenges to designers and motivates to verify a system and consequently debug errors already in early phases of the design process, e.g. at the Electronic System Level (ESL). To this end, several methods and tools such as assertion checkers, property checkers, symbolic executers, and more have been proposed. However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose the idea of a generic error localization methodology, which aids the designer in error localization without the need to change the respectively utilized verification method. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today (including possible updates and newly proposed ones in the future). The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.

A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System

Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng

National Central University, Taiwan

Since 2011, due to the growth in the amount of information, the innovation of learning algorithms and the improvement of computer technology make the application of artificial intelligence feasible in a wide range of fields. This paper presents a sketch classifier technique with deep learning models. We use the depth-wise convolution layer to lighten the deep neural network. The result shows the improvement in approximately 1/5 of computation. We use Google Quick Draw dataset to train and evaluate the network, which can have 98% accuracy in 10 categories and 85% accuracy in 100 categories. Finally, we realize it on STM32F469I Discovery development board for demonstration. The system can achieve real-time implementation of sketch classification.

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers

Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh

National Cheng Kung University, Taiwan

Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. Resolving conflicts is non-trivial due to the fact that the memory access pattern of the detection task depends on the trained result. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.

Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems

Ching-Hwa Cheng

Feng Chia University, Taiwan

A built-in digitalized power management (DPMM) and voltage domain programmable (VDP) mechanisms are proposed to design a low-power system. In the proposed techniques, the high and low voltages applied to logic modules can be switchable. This flexible voltage-domain assignment allows the chip performance and power consumption can dynamically adjust during circuit operation. To support the DPMM and VDP mechanisms, the voltage-level monitor circuit and power-switch circuit are designed to support multiple operation modes for DPMM-VDP digital circuit designs. A powerless retention flip-flop is developed for temporary data storage during voltage domain dynamically switching. While to prevent the system failure come from voltage integrity problem, a built-in voltage-level monitoring mechanism is utilized to monitor voltage integrity during VDP circuit operation. The proposed mechanism allows the chip performance and power consumption to be flexibly adjusted during circuit operation. Two physical implementation chips and measured results proof of this methodology has 30~55% power reduction comparisons with using single-Vdd.

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

Martin Stava

Brno University of Technology, Czech Republic

This paper presents a novel online fault tolerance method for network-on-chip interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. The other concept of monitoring errors separately on two types of interconnects [3] – inter-switch links and intra-switch input/output port paths – is also employed. Both the concepts allow more efficient routing when compared to existing error recovery schemes. Experimental validation shows that the proposed scheme delivers better or at least similar performance when compared to existing NoC error recovery schemes.

Fault-Aware Performance Assessment Approach for Embedded Networks

Jan Malburg1, Karl Janson2, Jaan Raik2, Frank Dannenmann1

1German Aerospace Center, Bremen, Germany; 2TalTech, Tallinn, Estonia

Current embedded systems are more and more using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4x4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.

Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung-Han Tsai1, Yuan-Chen Ho1, Ming-Hwa Sheu2

1National Central University, Taiwan; 2National Yunlin University of Science and Technology

At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages on low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.

4:00pm - 4:30pmIndustrial Session: Trends and Challenges in Automotive Semiconductor Development
Session Chair: Paolo Bernardi, Politecnico Di Torino
Doubletree by Hilton City Plaza 

Trends and Challenges in Automotive Semiconductor Development

Charlotte Rohr


4:30pm - 6:00pmSpecial Session: From Constraints to Tape-Out: Towards a Continuous AMS Design Flow
Session Chair: Manfred Dietrich, Dikuli Unternehmensberatung
Doubletree by Hilton City Plaza 

Flexible Generation of Analog Integrated Layouts Using a Novel Floorplanning-Driven P&R Approach

Benjamin Prautsch1, Uwe Hatnik1, Jens Lienig2, Jens Benndorf3

1Fraunhofer IIS/EAS Dresden; 2TU Dresden; 3Dream Chip Technologies GmbH

A fault-free and verified layout is the final result of the analog design flow. One approach particular-ly aiding layout design is generator-based automation. Generators create layouts fast in a parame-terizable and structurally pre-defined bottom-up way. However, limited structural flexibility and limited access to formalized requirements are disadvantages of generators. This work introduces a new generator concept that allows a mixture of both recent bottom-up layout description and ab-stract top-down layout description. Both constructive and iterative algorithms that use formal con-straints as input aid the bottom-up and top-down styles, respectively. This way, we overcome limits of procedural generators and generation gets standardized in a template-based way. The new ap-proach bridges the gap between procedural bottom-up generators and optimization-based top-down approaches being a step towards a continuous analog design automation flow.

Invasive Analysis Framework for non-functional Effect Verification

Georg Gläser1, Martin Grabmann1, Dirk Nuernbergk2

1IMMS GmbH; 2Melexis GmbH

Modern methods for system analysis and verification demand for either refining a given model or evaluating the impact of certain changes as for instance in design space exploration. In Ana-log/Mixed-Signal systems the hand-made models show the purely functional behavior. For includ-ing non-functional effects such as sensitivity for power supply non-idealities, the models have to be refined. In this contribution, we present a framework for processing Verilog-AMS models. This framework can be used to structurally modify a given system and interface to an industrial simula-tion environment for paving the way to novel analysis and refinement methods. We demonstrate our framework by introducing a method for automated extraction of operating condition checks to system level. In addition, a method for analyzing the impact of parasitic elements in a layout ex-tracted netlist and include a discussion about further potential applications of invasive analysis in AMS systems.

Resolving Dependencies in Hierarchical AMS Designs Using Constraint Propagation and Budgeting

Andreas Krinke1, Tilman Horst1, Jens Lienig1, Goeran Jerke2

1TU Dresden; 2Robert Bosch GmbH

Complex global dependencies complicate the separate design of individual modules, because de-sign decisions in one module may influence and ultimately violate constraints in other modules. In this work, we propose a methodology to make constraints visible and verifiable in all relevant mod-ules throughout the hierarchy. The constraints from the system specification as well as those added later by designers are propagated within the design hierarchy. At the end of this process, we know the set of relevant constraints including, e.g., geometrical dimensions and pin positions, for every module. If the final layout fulfills all these constraints, the correct operation of the overall system according to the specification can be guaranteed.

Schematic Generation Framework in a Mixed Signal Top Down Design Flow

Tobias Markus1, Markus Mueller2, Ulrich Brue-ning3

1ZITI University Heidelberg; 2Extoll GmbH; 3Universität Heidelberg

This work demonstrates an important step inside the Mixed-Signal Top-Down Design Flow which focuses on the schematic generation framework from the System-Level Model. The structural hier-archy and schematics for the Full Custom part are generated from the System-Level SystemVerilog RNM model. Furthermore, the developed method offers a framework which automatically detects general models in the leaf cells and runs corresponding dimensioning scripts. The framework is flexible and calls user defined dimensioning scripts which can range from simple scripts to abstract approaches. The flow was used with great success in eliminating structural inconsistencies, related errors and avoiding additional rework. Additionally, it provides high automation which reduces the design time.

6:30pm - 8:00pmWelcome dinner
Doubletree by Hilton City Plaza 
Date: Thursday, 25/Apr/2019
8:30am - 10:00amSession 2: On-line Test & Reliability
Session Chair: Alberto Bosio, ECL INL
Doubletree by Hilton City Plaza 

Hybrid On-line Self-test Architecture for Computational Units on Embedded Processor Cores

Andrea Floridia, Ernesto Sanchez, Davide Piumatti, Gianmarco Mongano

Politecnico di Torino, Italy

Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.

On the In-field Test of GPGPU Scheduler Memory

Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Stefano Di carlo

Politecnico di Torino, Italy

GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.

Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Marco Restifo1, Matteo Sonza Reorda1, Paolo Bernardi1, Felipe Almeida1, Deborah Calabrese1, Davide Appello2, Roberto Ugioli2, Vincenzo Tancorre2, Giulio Zoppi2

1Politecnico di Torino, Italy; 2STMicoelectronics, Italy

Automotive systems must reach a high reliability figure in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible manufacture defects that could appear during lifetime. Burn-In (BI) is a manufacturing test phase used screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing and stressing process of complex System on Chips (SoCs) using the in-field conditions. Final Test (FT) is the last step of the testing flow, which discovers a faulty device exited by all the previous stress phases. This paper aims at describing the motivations and the effectiveness for combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. This novel step intercept faults before the FT. Moreover, the paper analyses the required architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics evaluates the possible test time and cost reduction

10:00am - 10:30amPoster Session 2
Doubletree by Hilton City Plaza 

A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider

Hwann-Kaeo Chiou, Wei-Min Sung

Department of Electrical Engineering, National Central University, Taiwan

This paper presents a 5-10.5 GHz wideband fully-integrated I/Q transmitter in tsmcTM 90-nm CMOS technology. A current-mode passive mixer was adopted to enhance the linearity and low-power performance. The transmitter also integrated current-mode logic (CML) frequency divider (FD) to generate I/Q signals at LO-port. The I/Q signals were directly combined by using high-Q top-metal lines. An inductively coupled resonator (ICR) wideband output matching network was used to transform balance to unbalance output signal in RF drive-amplifier. The proposed transmitter achieves a 3-dB bandwidth from 5 to 10.5 GHz, a conversion gain of 12.9 dB, an output P1dB of -4.17 dBm, an output IP3 of 16.47 dBm, a carrier suppression of 30.02 dBc and a sideband suppression of 39.62 dBc under an LO power of 14 dBm at the center frequency of 8 GHz. The chip consumed dc power of 66.36 mW. The chip dimensions, including all RF and DC pads, are 1.25 ×1.1 mm2.

FPGA-based SIFT Implementation for Wearable Computing

Attila Fejér1,2, Zoltán Nagy1, Jenny Benois-Pineau2, Péter Szolgay1, Aymar de Rugy3, Jean-Philippe Domenger2

1Technology and Bionics, Pázmány Péter Catholic University Faculty of Information, Hungary; 2Laboratoire Bordelais de Recherche en Informatique, University of Bordeaux, France; 3Institut de Neurosciences Cognitives et Intégratives d'Aquitaine, University of Bordeaux, France

The article describes the first steps to achieve control over a robotic or prosthetic arm based on analysis of visual environment acquired in real-time by video cameras on glasses and on the prosthesis. One of the main goals of the research is to develop a wearable, portable, lightweight, and low power consumption device for visual scene analysis. This paper will discuss the critical steps of its implementation on an FPGA board.

We implemented some time-consuming parts of the SIFT algorithm needed for the analysis in C/C++ language on TUL PYNQ-Z2 FPGA board.

This implementation allows for a low power consumption of the programmable logic part of the system. The obtained value is 0.274W. Processing capacity is 96.45 images per second on a small wearable size device which allow for the real-time implementation of the whole analysis in the future.

Using Voters May Lead to Secret Leakage

Jan Belohoubek, Petr Fiser, Jan Schmidt

Czech technical University in Prague, Czech Republic

The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.

Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology

Martin Kovac, Daniel Arbet, Viera Stopjakova, Michal Sovcik

Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, Slovak Republic

This paper deals with cross-implementation of analytical and physical fundamentals of ultra low-voltage charge pumps. The analysis is based on precise, general formulas including characteristic parasitic effects valid for linear charge pumps. The parasitic effects are extended by nonlinear parasitic capacitances represented as equivalent linear model of a switched transistor itself. The discussion about nonlinear and linear behaviour of these parasitics is also included and demonstrated using cross-coupled, dynamic threshold implementation, where the EKV model of transistors has been utilized. The paper also introduced a new design rule for design of charge pumps based on transistors working in sub-threshold region to maximize the power throughput. This is achieved by tuning the operation conditions to the boundary case.

New Categories of Safe Faults in a Processor-Based Embedded System

Davide Piumatti1, Matteo Sonza Reorda1, Cemil Cem Gursoy2, Maksim Jenihhin2, Stephen Oyeniran2, Jaan Raik2, Raimund Ubar2

1Politecnico di Torino, Dip. Automatica e Informatica - Torino, Italy; 2Tallinn University of Technology - Tallinn, Estonia

The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some new classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults associated belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed approach requires an analysis of the processor at the RT level and the use of an ATPG tool with specific constraints on Primary Inputs (PIs) or Primary Output (POs) of some units inside the processor. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.

10:30am - 12:00pmSession 3: Analog Circuit Design & Test
Session Chair: Witold Pleskacz, Warsaw University of Technology
Doubletree by Hilton City Plaza 

High Side Power MOSFET Switch Driver for a Low-power AC/DC Converter

Miroslav Potočný, Juraj Brenkuš, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic

With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions need to be provided. In this paper, we propose a solution that is optimized for operation with output loads up to 500 mW, while high efficiency and close to zero no-load consumption have been our foremost design goals. The proposed design is implemented in a high-voltage CMOS process and transistor level simulation results show improved properties of the proposed solution over the existing ones.

Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Viera Stopjakova

Slovak University of Technology, Slovak Republic

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in standard twin-well 130 nm CMOS technology. The nominal power supply voltage was set to V DD = 0.4 V and the working temperature range was set to industrial standard -20 ◦ C – 85 ◦ C. The proposed comparator design is intended to work in energy harvesting system. Hence, low power consumption is a key requirement. It employs bulk-driven transistors at the input stage and operates in so-called current mode. The addressed comparator circuit draws less then 5 μA in typical conditions but its function and robustness has been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

A New FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network

Sergei Odintsov1, Ludovica Bozzoli2, Corrado De Sio2, Luca Sterpone2, Artur Jutman1

1Tallinn University of Technology; 2Politecnico di Torino

Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA) with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various sub-systems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.

12:00pm - 1:30pmLunch
Doubletree by Hilton City Plaza 
1:30pm - 2:30pmKeynote 3
Session Chair: Zoran Stamenkovic, IHP
Doubletree by Hilton City Plaza 

Can New Defect Models Help Eliminate System Level Tests?

Adit D. Singh

Dept. of Electrical & Computer Engineering - Auburn University, US

ICs have long been tested for manufacturing defects using low cost scan tests. However, such structural tests no longer appear sufficient in ensuring the required test quality for complex processor SOCs. Expensive System Level Tests (SLTs), that temporarily mount the SOC on a test board closely replicating the target hardware application, are increasing being used to perform extensive functional testing as a final defect screen. In this talk we discuss the effectiveness of the advanced new defect models such as cell aware, timing aware cell aware, gate exhaustive, TSOF, etc. that have been introduced to improve the defect coverage of scan tests and thus minimize the need for SLTs. We also consider failure mechanisms that may be missed by even these new tests, in particular, timing failures resulting from an accumulation of the delays caused by random process variations.

3:00pm - 11:00pmSocial Event
Date: Friday, 26/Apr/2019
9:00am - 10:30amSession 4: HW Design for Communication Networks
Session Chair: Dominik Macko, Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava
Doubletree by Hilton City Plaza 

Modular Data Link Layer Processing for THz Communication

Lukasz Lopacinski1, Mohamed Hussein Eissa1, Goran Panic1, Alireza Hasani1,2, Rolf Kraemer1,2

1IHP – Leibniz-Institut für innovative Mikroelektronik, Germany; 2Brandenburgische Technische Universität Cottbus - Senftenberg

In this paper, we demonstrate a modular baseband and modular data link layer processors for wireless communication, which has been designed for a 200 GHz frontend. Although the individual system elements are well known, we combine the performance of parallel baseband and data link layer cores to cover a larger bandwidth. We combine three cores and achieve a single 1.5 GHz channel (3×500 MHz). This paper is focused on the digital elements of the demonstrator, especially on the data link layer aspects and field-programmable gate array (FPGA) processing.

Hash-based Pattern Matching for High Speed Networks

Tomáš Fukač, Jan Kořenek

Faculty of Information Technology Brno University of Technology, Czech Republic

Regular expression matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links and the number of regular expressions, pattern matching architectures have to be improved to retain wire-speed processing. Multi-striding is a well-known technique to increase processing speed but it requires a lot of FPGA resources. Therefore, we focus on the design of new hardware architecture for fast pre-filtering of network traffic. The proposed pre-filter performs fast hash-based matching of short strings, which are specific for matched regular expressions. As the proposed pre-filter significantly reduces input traffic, exact pattern matching can operate on significantly lower speeds. Than exact pattern match can be done by CPU or by a slow automaton with a few hardware resources.. The paper provides analyses false-positive detection of the pre-filter with respect to the length of matching strings. The number of false-positives are low, even if the length of selected strings is short.

Therefore input traffic can be significantly reduced. For 100 Gb links, the pre-filter reduced the input data to 1.83 Gbps using four-symbol strings.

Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic

Roman Vrána, Jan Kořenek, David Novák

Faculty of Information Technology, Brno University of Technology, Czech Republic

With the growing amount of encrypted network traffic, it is important to have tools for analysis and classification of encrypted network data. Encrypted network traffic is usually analysed by statistical methods, because Deep Packet Inspection or pattern matching is not applicable. However, the statistical methods are usually designed to work offline on already captured network traffic. For real-time analysis, hardware acceleration is needed to achieve wire-speed 10 Gbps throughput. Therefore, we focus on real-time monitoring of encrypted network traffic and propose new acceleration method to extract features from encrypted network data. Approximate computing is used to speed up computation of entropy for the input data stream and to reduce FPGA logic utilization. As can be seen in the results, the precision of classification has decreased only by 0.1 to 0.2%. Moreover, proposed hardware architecture has very low FPGA logic utilization and can operate at high frequency.

10:30am - 11:00amPoster Session 3
Doubletree by Hilton City Plaza 

Nonlinear Compression Codes Used In IC Testing

Ondrej Novak

TU Liberec, Czech Republic

Test patterns used to be transferred in a compressed form as it minimizes test access mechanism bandwidth and time. It was found that nonlinear binary codes can be used for encoding test patterns similarly as linear ones and the compression efficiency may be higher. The nonlinear binary codes can be constructed in such a way that the number of codeword bits is higher than it is for the linear code words while the maximum number of specified bits is preserved. The nonlinear binary codes can be used in test pattern decompressors. It causes that better encoding characteristics can be obtained for a higher number of parallel scan chains then it can get for decompressors with linear codes. In this paper, the benefits and costs are quantified. Suboptimal nonlinear codes are found by a heuristic algorithm. They are implemented in test pattern decompressors, and the random pattern and benchmark circuit pattern encodability are verified.

Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI’s Components using RAD-THERM TCAD Subsystem

Konstantin Petrosyants1, Maxim Kozhukhov2, Dmitry Popov1

1National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia; 2JC ‘VNIIEM Corporation’, Moscow, Russia

A special RAD-THERM version of TCAD subsystem based on Sentaurus Synopsys platform taking into account different types of irradiation (gamma-rays, neutrons, electrons, protons, single events) and external/internal heating effects was developed and validated to forecast the results of natural experiments, and help the designer on with reliability guarantee. The radiation- and temperature-induced faults were modeled and simulated for Si/SiGe BJTs/HBTs and bulk/SOI MOSFETs as BiCMOS LSI’s components. The causes of device parameter degradation were discussed.

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430

Karel Szurman, Zdenek Kotasek

Faculty of Information Technology, Brno University of Technology, Czech Republic

Reconfigurable fault tolerant (FT) architecture can be implemented into a SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. Therefore, SEU mitigation strategy is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and thus, to perform implemented functionality after the occurrence of a fault. In this paper, we propose a run-time reconfigurable FT architecture based on coarse-grained TMR with triplicated soft-core processor NEO430 core, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when the reconfiguration of a failed processor instance was finished into the state where all three processors operate synchronously. The paper describes implemented FT architecture and run-time fault recovery strategy performing all necessary steps without additional blocking of the system functionality. The state synchronization for the soft-core processor NEO430 architecture is described in a further detail. Moreover, the paper presents developed PDR framework used for validation and testing of proposed fault recovery strategy.

Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime

Kai-Hsun Chen2, Ching-Yuan Chen1, Jiun-Lang Huang1,2

1Graduate Institute of Electronics Engineering (GIEE), National Taiwan University, Taipei, Taiwan; 2Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

The reconvergence structure among the digital circuit has long been recognized as the main reason for the ATPG backtrack which hurts its performance. We also found that the reconvergence structure induces not only more but also prolonged backtracks and cause more severe performance degradation than expected. Therefore, we proposed a new testability measure that considers reconvergence to guide the ATPG justification process. Our experimental results show that for benchmark circuits and some in-house industrial designs, the proposed method significantly decreases the runtime of the ATPG process, especially for those with deep logic level, by up to 76%. Also, the proposed method could easily be integrated into a wide variety of existing ATPG frameworks.

Comparison of Nearest Neighbours Algorithms for PET Image Reconstruction on FPGA

Zoltan Nagy1, Andras Kiss1, Levente Mark Santha1,2, Kristof Karacs1

1Pázmány Péter Catholic University, Budapest, Hungary; 2Institute for Computer Science and Control Hungarian Academy of Sciences, Budapest, Hungary

Medical image reconstruction is still an important field, where more and more effort are taken in order to make faster and more detailed images. Usually 10-100Gbyte data are collected from a PET scanning and examined offline. By applying a preprocessing step near the sensor layer the input data of the image reconstruction algorithm can be largely reduced, therefore lesser bandwidth is needed. By knowing the correction parameters of the sensors several prefiltering can be applied next to the sensor. FPGA seems to be a good platform to handle the preprocessing, because it can have large computation performance with low power consumption, and can easily reconfigure in order to apply different filtering on the input events.

A Global Sensitivity Analysis Method Based on Local Regression

Ingrid Kovacs1, Alexandra Iosub2, Marina Topa1, Andi Buzo3, Georg Pelz3

1Technical University of Cluj-Napoca, Romania; 2Gheorghe Asachi Technical University of Iași, Romania; 3Infineon Technologies AG, Neubiberg, Germany

Most sensitivity analysis methods from literature impose specific experiment plans (design-of-experiments). Moreover, the size of the experiment plan, which is in conjunction with the number of system evaluations, increases with the number of factors that may affect the systems’ behavior. This paper introduces a gradient-based global sensitivity analysis method which overcomes these limitations. First, its performance is compared against six sensitivity analysis methods on sets of polynomial test functions. The comparison is carried out by means of the number of system evaluations implied and the reported factor ranking list. The proposed method proved to have comparable accuracy to the best of the six known methods- the EFAST method- with the advantage of a lower number of system evaluations. These two methods are further applied on an electronic system, an E-Bike application. In this case, the proposed method employs the verification plan of the EFAST method, as well as a standard Monte Carlo experiment plan with about one third of the system evaluations of the EFAST. Even with a much lower number of system evaluations, the proposed method yields the same result as the EFAST method in terms of the factor ranking list.

11:00am - 12:30pmSession 5: Student Session
Session Chair: Ondrej Novak, TU Liberec
Doubletree by Hilton City Plaza 

Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter

Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold Adam Pleskacz

Warsaw University of Technology, Poland

This paper presents the design of an oscillator-based true random number generator. The operation of the presented TRNG architecture is based on sampling a high-frequency oscillator output with a clock generated by a low-frequency noisy oscillator. The recycling folded cascode architecture was used for low power noise amplifier. A new method to achieve higher jitter in the low frequency oscillator is presented. The bit rate of the designed TRNG is 1.02 Mb/s. The circuit power consumption is 67 µW. The results of the simulations and statistical tests of the designed random number generator are also presented in this paper.

Analyzing and Optimizing the Dummy Rounds Scheme

Stanislav Jeřábek, Jan Schmidt

Czech Technical University in Prague, Czech Republic

The dummy rounds protection scheme, intended to offer resistance against Side Channel Attacks to Feistel and SP ciphers, has been introduced in earlier work. Its experimental evaluation revealed weaknesses, most notably in the first and last round. In this contribution, we show that the situation can be greatly improved by controlling the transition probabilities in the state space of the algorithm.

We derived necessary and sufficient conditions for the round execution probabilities to be uniform and hence the minimum possible. The optimum trajectories over the state space are regular and easy to implement.

Automated Integration of Dynamic Power Management into FPGA-Based Design

Michal Škuta, Dominik Macko

Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava, Slovak Republic

A low power or energy efficient hardware operation is nowadays gaining attention. It is especially true for battery-operated or energy-harvesting devices, such as most of the Internet of Things end nodes. For specific applications with rather limited market, the FPGAs are very good alternative. However, evolution of these devices is focused on high-level programming, giving application designers space to focus on application function rather than to be concerned about its low-level implementation on FPGA device - it is handled by automation tools. Thus, new FPGA-application designers are nowadays not very familiar with hardware aspects and it is difficult for them to apply power-reduction techniques in order to create an energy-efficient system. This paper is focused on automation of power-management integration into the FPGA-application design based on abstract specification, which is easy-to-use even for unfamiliar designers. It simplifies and speeds-up the low-power and energy-efficient FPGA-application design process. Moreover, the automation prevents many human-errors and thus it also alleviates the verification process. Experimental results indicate that the proposed power-management scheme is working correctly and it can be automatically generated.

Development of Wearable Hardware Platform to Measure the ECG and EMG with IMU to Detect Motion Artifacts

Muhammad TANWEER, Kari Halonen

Aalto University, Finland

Weareable biomedical devices make it possible to monitor physiological parameters of human beings where physical fitness is critical for their work. However, the motion artifacts corrupt the ambulatory measurements of electrophysiological parameters and it is necessary to detect and eliminate these motion artifacts. The long term measurement and analysis of health parameters require enormous data processing and storage resources on board. It is also challenging to perform sensor fusion of multiple devices and to manage multiple communication channels. This paper describes the development of a wearable hardware platform to measure electrocardiogram (ECG) and electromyogram (EMG) with an additional IMU sensor to detect the motion artifacts. Bringing all the sensors on single platform resolves the sensor fusion problems. The measurements are digitized and sent wirelessly through a bluetooth interface to a remote unit in real-time. Where extensive processing and analysis algorithms are applied to detect motion artifacts and extract The features of the ECG and EMG waveform structures.

12:30pm - 2:00pmLunch
Doubletree by Hilton City Plaza 
2:00pm - 3:30pmSession 6: HW Design at Application-Level
Session Chair: Petr Fišer, Czech Technical University in Prague
Doubletree by Hilton City Plaza 

Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines

Vlad Muresan, Mihail Abrudean

UTCN, Romania

In this paper, a solution to control the servicing machines of a rotary hearth furnace is presented. The proposed control strategy is based on the usage of a modified cascade control structure. The proposed control solution is augmented with a fault detection system capable to detect the faults which frequently occur in the operation of the D.C. motors used to drive the servicing machines. It is proved through simulation that, in a certain range of faults magnitude, their effect is rejected by the controllers, aspect which makes the proposed control system a fault tolerant one. Also, due to the usage of neural reference model, the faults magnitude can be quantified and when the safety limits are reached, some decisions for reducing the servicing machines operation are automatically generated.

Hardware and Control Design of a Ball Balancing Robot

Ioana Lal1, Marius Nicoara1, Alexandru Codrean2, Lucian Busoniu2

1Robert Bosch, Romania; 2Technical University of Cluj-Napoca, Romania

This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and agility lead to the choice of ball, motors, gears, omnidirectional wheels, and body frame. The electronic hardware architecture is presented in detail, together with timing results showing that real-time control can be achieved. Finally, we design a linear quadratic regulator for balancing, starting from a 2D model of the robot. Experimental balancing results are satisfactory, maintaining the robot in a disc 0.3 m in diameter.

A hardware friendly rational function approximation evaluator

Silviu-Ioan Filip

Inria, France

In this talk I will present an automatic method for the high throughput evaluation of functions via polynomial or rational approximations and its hardware implementation, on FPGAs. These approximations are evaluated using Ercegovac’s iterative E-method adapted for FPGA implementation. We discuss how the polynomial and rational function coefficients are optimised so that they satisfy the constraint of the E-method. We present several examples of practical interest; in each case a resource-efficient approximation is proposed and comparisons are made with alternative approaches.

3:30pm - 4:00pmClosing Session
Doubletree by Hilton City Plaza 

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