Nonlinear Compression Codes Used In IC Testing
TU Liberec, Czech Republic
Test patterns used to be transferred in a compressed form as it minimizes test access mechanism bandwidth and time. It was found that nonlinear binary codes can be used for encoding test patterns similarly as linear ones and the compression efficiency may be higher. The nonlinear binary codes can be constructed in such a way that the number of codeword bits is higher than it is for the linear code words while the maximum number of specified bits is preserved. The nonlinear binary codes can be used in test pattern decompressors. It causes that better encoding characteristics can be obtained for a higher number of parallel scan chains then it can get for decompressors with linear codes. In this paper, the benefits and costs are quantified. Suboptimal nonlinear codes are found by a heuristic algorithm. They are implemented in test pattern decompressors, and the random pattern and benchmark circuit pattern encodability are verified.
Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI’s Components using RAD-THERM TCAD Subsystem
1National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia; 2JC ‘VNIIEM Corporation’, Moscow, Russia
A special RAD-THERM version of TCAD subsystem based on Sentaurus Synopsys platform taking into account different types of irradiation (gamma-rays, neutrons, electrons, protons, single events) and external/internal heating effects was developed and validated to forecast the results of natural experiments, and help the designer on with reliability guarantee. The radiation- and temperature-induced faults were modeled and simulated for Si/SiGe BJTs/HBTs and bulk/SOI MOSFETs as BiCMOS LSI’s components. The causes of device parameter degradation were discussed.
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430
Faculty of Information Technology, Brno University of Technology, Czech Republic
Reconfigurable fault tolerant (FT) architecture can be implemented into a SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. Therefore, SEU mitigation strategy is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and thus, to perform implemented functionality after the occurrence of a fault. In this paper, we propose a run-time reconfigurable FT architecture based on coarse-grained TMR with triplicated soft-core processor NEO430 core, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when the reconfiguration of a failed processor instance was finished into the state where all three processors operate synchronously. The paper describes implemented FT architecture and run-time fault recovery strategy performing all necessary steps without additional blocking of the system functionality. The state synchronization for the soft-core processor NEO430 architecture is described in a further detail. Moreover, the paper presents developed PDR framework used for validation and testing of proposed fault recovery strategy.
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime
1Graduate Institute of Electronics Engineering (GIEE), National Taiwan University, Taipei, Taiwan; 2Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
The reconvergence structure among the digital circuit has long been recognized as the main reason for the ATPG backtrack which hurts its performance. We also found that the reconvergence structure induces not only more but also prolonged backtracks and cause more severe performance degradation than expected. Therefore, we proposed a new testability measure that considers reconvergence to guide the ATPG justification process. Our experimental results show that for benchmark circuits and some in-house industrial designs, the proposed method significantly decreases the runtime of the ATPG process, especially for those with deep logic level, by up to 76%. Also, the proposed method could easily be integrated into a wide variety of existing ATPG frameworks.
Comparison of Nearest Neighbours Algorithms for PET Image Reconstruction on FPGA
1Pázmány Péter Catholic University, Budapest, Hungary; 2Institute for Computer Science and Control Hungarian Academy of Sciences, Budapest, Hungary
Medical image reconstruction is still an important field, where more and more effort are taken in order to make faster and more detailed images. Usually 10-100Gbyte data are collected from a PET scanning and examined offline. By applying a preprocessing step near the sensor layer the input data of the image reconstruction algorithm can be largely reduced, therefore lesser bandwidth is needed. By knowing the correction parameters of the sensors several prefiltering can be applied next to the sensor. FPGA seems to be a good platform to handle the preprocessing, because it can have large computation performance with low power consumption, and can easily reconfigure in order to apply different filtering on the input events.
A Global Sensitivity Analysis Method Based on Local Regression
1Technical University of Cluj-Napoca, Romania; 2Gheorghe Asachi Technical University of Iași, Romania; 3Infineon Technologies AG, Neubiberg, Germany
Most sensitivity analysis methods from literature impose specific experiment plans (design-of-experiments). Moreover, the size of the experiment plan, which is in conjunction with the number of system evaluations, increases with the number of factors that may affect the systems’ behavior. This paper introduces a gradient-based global sensitivity analysis method which overcomes these limitations. First, its performance is compared against six sensitivity analysis methods on sets of polynomial test functions. The comparison is carried out by means of the number of system evaluations implied and the reported factor ranking list. The proposed method proved to have comparable accuracy to the best of the six known methods- the EFAST method- with the advantage of a lower number of system evaluations. These two methods are further applied on an electronic system, an E-Bike application. In this case, the proposed method employs the verification plan of the EFAST method, as well as a standard Monte Carlo experiment plan with about one third of the system evaluations of the EFAST. Even with a much lower number of system evaluations, the proposed method yields the same result as the EFAST method in terms of the factor ranking list.