Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

Session Overview
Session 2: On-line Test & Reliability
Thursday, 25/Apr/2019:
8:30am - 10:00am

Session Chair: Alberto Bosio, ECL INL
Location: Doubletree by Hilton City Plaza

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ID: 119 / Session 2: 1
Regular Paper
Topics: Test, DfT, Diagnosis, Dependability and Safety of Digital Circuits and Systems
Keywords: Software-Based Self-Test, On-line Testing, Hybrid Test, Safety-critical Applications

Hybrid On-line Self-test Architecture for Computational Units on Embedded Processor Cores

Andrea Floridia, Ernesto Sanchez, Davide Piumatti, Gianmarco Mongano

Politecnico di Torino, Italy

Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.

ID: 137 / Session 2: 2
Regular Paper
Topics: Test, DfT, Diagnosis, Dependability and Safety of Digital Circuits and Systems
Keywords: GPGPUs, SBST, memory testing

On the In-field Test of GPGPU Scheduler Memory

Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Stefano Di carlo

Politecnico di Torino, Italy

GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.

ID: 143 / Session 2: 3
Industrial Paper
Topics: Test, DfT, Diagnosis, Dependability and Safety of Digital Circuits and Systems
Keywords: Burn-In, System Level Test, Test Flow, Automotive, Safety-Critical Application

Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Marco Restifo1, Matteo Sonza Reorda1, Paolo Bernardi1, Felipe Almeida1, Deborah Calabrese1, Davide Appello2, Roberto Ugioli2, Vincenzo Tancorre2, Giulio Zoppi2

1Politecnico di Torino, Italy; 2STMicoelectronics, Italy

Automotive systems must reach a high reliability figure in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible manufacture defects that could appear during lifetime. Burn-In (BI) is a manufacturing test phase used screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing and stressing process of complex System on Chips (SoCs) using the in-field conditions. Final Test (FT) is the last step of the testing flow, which discovers a faulty device exited by all the previous stress phases. This paper aims at describing the motivations and the effectiveness for combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. This novel step intercept faults before the FT. Moreover, the paper analyses the required architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics evaluates the possible test time and cost reduction

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