Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
Session Overview
Date: Thursday, 25/Apr/2019
8:30am
-
10:00am
Session 2: On-line Test & Reliability
Location: Doubletree by Hilton City Plaza
Chair: Alberto Bosio, ECL INL
 

Hybrid On-line Self-test Architecture for Computational Units on Embedded Processor Cores

Andrea Floridia, Ernesto Sanchez, Davide Piumatti, Gianmarco Mongano

Politecnico di Torino, Italy



On the In-field Test of GPGPU Scheduler Memory

Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Stefano Di carlo

Politecnico di Torino, Italy



Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Marco Restifo1, Matteo Sonza Reorda1, Paolo Bernardi1, Felipe Almeida1, Deborah Calabrese1, Davide Appello2, Roberto Ugioli2, Vincenzo Tancorre2, Giulio Zoppi2

1: Politecnico di Torino, Italy; 2: STMicoelectronics, Italy

10:00am
-
10:30am
Poster Session 2
Location: Doubletree by Hilton City Plaza
 

A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider

Hwann-Kaeo Chiou, Wei-Min Sung

Department of Electrical Engineering, National Central University, Taiwan



FPGA-based SIFT Implementation for Wearable Computing

Attila Fejér1,2, Zoltán Nagy1, Jenny Benois-Pineau2, Péter Szolgay1, Aymar de Rugy3, Jean-Philippe Domenger2

1: Technology and Bionics, Pázmány Péter Catholic University Faculty of Information, Hungary; 2: Laboratoire Bordelais de Recherche en Informatique, University of Bordeaux, France; 3: Institut de Neurosciences Cognitives et Intégratives d'Aquitaine, University of Bordeaux, France



Using Voters May Lead to Secret Leakage

Jan Belohoubek, Petr Fiser, Jan Schmidt

Czech technical University in Prague, Czech Republic



Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology

Martin Kovac, Daniel Arbet, Viera Stopjakova, Michal Sovcik

Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, Slovak Republic



New Categories of Safe Faults in a Processor-Based Embedded System

Davide Piumatti1, Matteo Sonza Reorda1, Cemil Cem Gursoy2, Maksim Jenihhin2, Stephen Oyeniran2, Jaan Raik2, Raimund Ubar2

1: Politecnico di Torino, Dip. Automatica e Informatica - Torino, Italy; 2: Tallinn University of Technology - Tallinn, Estonia

10:30am
-
12:00pm
Session 3: Analog Circuit Design & Test
Location: Doubletree by Hilton City Plaza
Chair: Witold Pleskacz, Warsaw University of Technology
 

High Side Power MOSFET Switch Driver for a Low-power AC/DC Converter

Miroslav Potočný, Juraj Brenkuš, Viera Stopjaková

Slovak University of Technology in Bratislava, Slovak Republic



Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Viera Stopjakova

Slovak University of Technology, Slovak Republic



A New FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network

Sergei Odintsov1, Ludovica Bozzoli2, Corrado De Sio2, Luca Sterpone2, Artur Jutman1

1: Tallinn University of Technology; 2: Politecnico di Torino

12:00pm
-
1:30pm
Lunch
Location: Doubletree by Hilton City Plaza
1:30pm
-
2:30pm
Keynote 3
Location: Doubletree by Hilton City Plaza
Chair: Zoran Stamenkovic, IHP
 

Can New Defect Models Help Eliminate System Level Tests?

Adit D. Singh

Dept. of Electrical & Computer Engineering - Auburn University, US

3:00pm
-
11:00pm
Social Event

 
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Conference: DDECS 2019
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